Instruction Generation for Hybrid Reconfigurable Systems

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Instruction Generation for Hybrid Reconfigurable
Systems

• Ryan Kastner, Seda Ogrenci-Memik,
• Elaheh Bozorgzadeh and Majid Sarrafzadeh
• kastner,seda,elib,majid_at_cs.ucla.edu

Embedded and Reconfigurable Systems
Group Computer Science Department UCLA Los
Angeles, CA 90095
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Outline

• Introduction
• Programmability
• Hybrid Reconfigurable Systems
• Strategically Programmable System
• Instruction Generation
• Uses in Hybrid Reconfigurable Systems
• Relation to Template Generation and Matching
• Algorithm for Template Generation and Matching
• Experiments
• Conclusion

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Programmability

• Future systems need programmability multiple
  levels of computation hierarchy
• Computational Hierarchy

Control
Control
ADD
Register
FU
Memory
FU
Register Bank
MUL
Register
?-Architecture Level
Architecture Level
Gate Level
Programmability Bit Byte Instruction (8 128 bits)
Basic Unit of Computation Boolean Operation (and, or, xor) Arithmetic Operation Functional Operation
Communication Direct wires connections Bundles of wires, registers Bus, memory
Hybrid Reconfigurable Systems have
programmability at one or more levels
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Tradeoffs
Control
Control
ADD
Register
FU
Memory
FU
Register Bank
MUL
Register
Architecture level
Micro-architecture level
Gate level
Types of Programmable Units
Custom instructions, Register banks
Datapath unit, Control unit, RAM
CLBs, LUTs
Example Platform
Hybrid Reconfigurable Systems should find a happy
medium
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SPS - Strategically Programmable System

• Embed (hard or soft) computational units
  Versatile Programmable Blocks (VPB) - into
  FPGA-like fabric
• Combine programmable units from gate,
  microarchitecture and architecture levels
• Balance flexibility and configuration time

• Need automated method of determining the
  functionality of VPBs

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Overview of SPS
SPS Compiler
Set of applications specified in high level code
(c/c, fortran, MOC)

• Compile to low
• level specification
• Determine VPB
• functionality

SPS Architecture
SPS Architecture Generation
SPS Module Placement
VPB Synthesis
Routing Arch.
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VPB Instruction Generation

• Given a set of applications, what computation
  should be implemented on VPBs?

RAM
VPB
VPBs?
RAM
VPB

• Want complex, commonly occurring computation
  patterns
• Look for computational patterns at the
  instruction level
• Basic operation is add, multiply, shift, etc.

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Problem Definition

• Determining VPB functionality requires regularity
  extraction
• Regularity Extraction - find common
  sub-structures (templates) in one or a collection
  of graphs
• Each application can be specified by collection
  of graphs (CDFGs)
• Templates are implemented as VPBs
• Two related sub-problems
• Template Matching
• Template Generation

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Template Matching Formal Defn

• Problem 1 Given a directed, labeled graph G(N,
  A), a library of templates, each of which is a
  directed labeled graph Ti(V,E), find every
  subgraph of G that is isomorphic to any Ti

Templates T
T1
T2
T3
T6
T4
T5
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Template Matching Formal Defn

• Problem 2 Given an infinite number of each set
  of templates ? T1, , Tk and an overlapping
  set of subgraphs of the given graph G(N,E) which
  are isomorphic to some member of ? minimize k as
  well as ? xi where xi is the number of templates
  of type Ti used such that the number of nodes
  left uncovered is the minimum.

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Template Generation

• Templates may not always be given as input
• An automatic regularity extraction algorithm must
  develop its own templates
• Generate a set of templates such that
• Number of templates is minimized
• Covering of the graph is maximized

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Related Work

• Useful in a wide variety of CAD applications
• Data path regularity
• Chowdhary98, Callahan99
• Scheduling Ly95
• System partitioning Rao93
• Low power design Mehra96
• Soft macros CPR Cadambi99 for PipeRench
  architecture

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An Algorithm for Simultaneous Template Generation
and Matching
Formal Definition
Informal Definition

• Given a labeled digraph G(V, E)
• C is a set of edge types
• C ? ?
• while (stop_conditions_not_met(G))
• C ? profile_graph(G)
• cluster_common_edges(G, C)

1. Find the most common edge type
2. Contract common edges
3. Repeat until stopping condition met

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Explanation of Algorithm

• Profile Edges Find most common edge types

Most Common Edge Type

• Edge contraction Merge adjacent nodes and
  maintain connectivity

Contract Edge

• Stopping Conditions
• Reach certain number of templates
• Graph sufficiently covered
• No frequently occurring edge type

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Algorithm in Action
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Algorithm Summary

• Algorithm can be generalized and used in a
  variety of applications
• Easily extended to hypergraphs
• Input/output pin restrictions can easily be added
• Performs template generation and matching
  simultaneously

We target algorithm towards VPB generation in SPS
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Experimental Setup
Control Flow Graph
Set of applications specified in C
SUIF Machine-SUIF
Dataflow Graph Generation Pass
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Experimental Setup
Compile to CDFGs
Perform Template Generation and Matching
Gather Statistics Graph Coverage, Num. Templates
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Experimental Setup - Benchmarks

• Selected files from MediaBench

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Similarity Across Applications
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Experimental Results

• Techniques
• Simple restrict templates to two operations
• No restrictions unlimited amount of operations
• Stopping condition most common edge occurs lt x
  (x?5-25)

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Summary

• Systems need programmability at multiple levels
  of the computational hierarchy
• Introduced SPS as a Hybrid Reconfigurable System
• Developed an instruction generation algorithm to
  determine VPB functionality
• Showed that common templates can be found across
  a similar set of applications
• An efficient covering possible using simple
  templates
• Future work Create methods to uncover more
  complex templates