Ultra LowPower Hybrid and Reconfigurable Computing

1
Pleiades
Ultra Low-Power Hybrid and Reconfigurable
Computing
PI Jan M. Rabaey
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The Energy-Flexibility Gap
1000
Dedicated HW
100
Energy Efficiency MOPS/mW (or MIPS/mW)
10
1
0.1
Flexibility (Coverage)
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Reconfigurable ComputingMerging Efficiency and
Versatility
Spatially programmed connection of processing
elements.
Hardware customized to specifics of
problem. Direct map of problem specific dataflow,
control. Circuits adapted as problem
requirements change.
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Matching Computation and Architecture
Two architectural models sequential control
data-driven
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Multi-granularity Reconfigurable Architecture
The Berkeley Pleiades Approach

• Computational kernels are spawned to satellite
  processors
• Control processor supports RTOS and
  reconfiguration
• Order(s) of magnitude energy-reduction over
  traditional programmable architectures

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Architecture Comparison
LMS Correlator at 1.67 MSymbols Data
Rate Complexity 300 Mmult/sec and 357 Macc/sec
16 Mmacs/mW!
Note TMS implementation requires 36 parallel
processors to meet data rate - validity
questionable
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Maia Reconfigurable Baseband Processor for
Wireless
79.7 of VSELP Code maps onto Reconfigurable
Processor Array 1 mW Power Dissipation
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Maia Implementation

• 0.25um tech 5.2mm x 6.7mm
• 1.2 Million transistors
• 40 MHz at 1V
• Hardware
• 1 ARM-8
• 8 SRAMs 8 AGPs
• 2 MACs
• 2 ALUs
• 2 In-Ports and 2 Out-Ports
• 4x8 FPGA
• Tape-out May 6, 1999

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Pleiades Research Areas

• System Architecture and Applications
• Domain-specific architecture definition and
  implementation
• Low-Power Reconfigurable Modules
• Low-energy FPGA, coarse-grain reconfigurable
  modules, interconnect
• Design Methodology and Software Development
• Methodology for reconfigurable architecture
  design OS for DVS and reconfiguration

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System Architecture and Applications

• Pleiades Overview
• The Pleiades Team
• Pleiades Satellite Communication Protocol
• Martin Benes

• Satellite Wrappers
• Data Steering Elements

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System Architecture and Applications

• Heterogeneous Module Integration
• Vandana Prabhu

EEPROM

• Off-chip Instruction/Data memory
• Intercom board for PC interface though Test Port
• Supply Voltages 2.5V(mem),1-1.2V(ARM),
  1V(Pleiades)
• Test mode to bypass ARM

MAIA
4Mb FT SyncSRAM 4.5ns cycle, 2.5V
PLEIADES
I/F
TEST PORT
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Low Power Modules

• Low-Energy ARM8 Chip-set - Tom Burd

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Low Power Modules

• Dynamic Voltage Scaling
• Trevor Pering and Tom Burd

Reduce processor speed to complete tasks on their
deadline and minimize energy
Time
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Low-Power Modules

• Low Energy Embedded FPGA
• Varghese George
• Test chip
• 8x8 CLB array
• 5 in - 3 out CLB
• 3-level interconnect hierarchy
• 4 mm2 in 0.25 mm ST CMOS
• 0.8 and 1.5 V supply
• Simulation Results
• 125 MHz Toggle Frequency
• 50 MHz 8-bit adder
• energy 70 times lower than comparable Xilinx

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Low-Power Modules

• Low-Energy Reconfigurable Interconnect
• Hui Zhang

Module-to-Module Connection Cost
Multiple-Bus
Energy (PJ)
Multiple-Bus
Multiple-Bus
0
1
3
4
5
6
7
8
2
9
10
Manhattan Distance (mm)
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Design Methodology and Software

• Reconfigurable Architecture Design Methodology
  - Marlene Wan
• Configurable Code Generation and Optimization -
  SueFei Li

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Design Methodology and Software

• RTOS synthesis for Reconfigurable Architectures
  - Roy Sutton