Interconnect Focus Center

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Variation Aware Design of On-Chip Optical Clock
Receiver Circuits
Nigel Drego Advisors Prof. Duane Boning, Prof.
Michael Perrott
MIT Microsystems Technology Laboratories
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Interconnect Focus Center
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Outline

• Introduction
• Past Work
• Goals
• Current Design
• Results
• Conclusions and Future Work

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Introduction Optical Interconnect

• Transmit signals optically on a single chip
  rather than between chips
• Potential advantages Reduced propagation delay,
  skew, jitter, crosstalk, and power
• Issues Variation introduces skew and jitter into
  optical networks as well

Key Focus Variation Robust Receiver Circuits
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Past Work

• S. Sam showed (1st Generation Receiver)
• Process and environmental variation contribute
  greatly to skew
• Baseline 0.25mm optical receivers were limited to
  frequencies below 1GHz
• A. Lum (2nd Generation Receiver)
• Employed bandgap reference for temperature-indepen
  dent biasing
• Voltage regulator increased immunity to VDD
  fluctuation
• VCSEL integration by wafer bonding (with C.
  Fonstad)
• Issues
• Skew due to process variation still too high
• Jitter, noise not characterized
• Receiver area large (205.5mm x 170mm)

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Current Design Goals

• Improve robustness to process variation
• More analysis/characterization
• Vary individual circuit parameters rather than
  solely relying on process corners
• Mismatch analysis
• Characterization of noise susceptibility and
  resultant jitter analysis
• Scale to higher frequencies while maintaining
  high sensitivities
• Reduce power, area

Key Focus Variation Robustness
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Current Design Circuit Topology

• Fully-differential architecture
• Employ common-mode and power-supply rejection
• Low-pass filtering easier, reduction in size of
  passives
• Enables common centroid layout
• Differential pair amplifiers with resistive loads
• Process-compensated current reference
• Need stable currents, not voltages (as bandgap
  reference provides)

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Current Design Input Stage

• Want low input-impedance node with high
  transimpedance gain

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Current Design Voltage Amplification Stages

• Resistive loads
• Resistor values lt 5k?, so area is not a major
  concern
• DC biasing set by current and resistor values
• Can achieve A ¼ 2-2.5 V/ V with 3dB bandwidth
  10GHz in 0.18mm CMOS
• Multiple stages (4-5) required before sending
  analog signal to inverters to be railed
• Reduces 3dB bandwidth to 3-3.5 GHz

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Current Design Amplifier Optimization

• Deep sub-micron transistors depart from
  square-law operation
• fT dependent on gm
• Use simulated gm curve of a single transistor and
  plot desired gain, swing versus current density !
  Width of device determined by load and desired
  bandwidth

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Current Design Process Compensated Current
Reference
Narendra et al. A Sub-1V Process-Compensated MOS
Current Generation Without Voltage Reference.
VLSI Digital Circuits. 2001.

• Want stable reference current from which bias
  currents are derived
• Bandgap reference provides stable reference
  voltage, but variation in bias transistors will
  result in variation in bias currents
• Process-compensated current reference (shown
  above) provides simple method of achieving
  variation-robust reference current

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Current Design Output Stage

• Cascaded inverters to rail analog signal to
  digital logic levels

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Results

• Circuit operates at 2GHz (10m A differential
  input photocurrent)
• Operation at 3GHz with increased optical power
  (due to gain roll-off)
• Preliminary skew analysis at process corners are
  encouraging
• 65ps skew between SS and TT corners (corresponds
  to 7.5 Lpoly and 23 VT) compared to gt100ps in
  previous design with smaller variation
• 120ps between SS and FF corners ! can we
  integrate deskew mechanisms now?
• More analysis and optimization to be done

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Conclusions and Future Work

• High frequency (gt2GHz) optical clock receivers
  are feasible
• Design techniques can help to increase robustness
  to process and environmental variation
• In-depth variation analysis will help to
  understand relation between circuit operation and
  variation sources
• Near term work
• Circuit optimization, layout
• Mismatch, noise analysis
• Longer term
• System-level analysis of variation sources in
  optical clock distribution networks
• Demonstration of complete, integrated optical
  clock distribution networks

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Acknowledgements

• MARCO Interconnect Focus Center
• Prof. Duane Boning, Prof. Mike Perrott
• Mike Mills, Joseph Panganiban, and Karen
  Gonzalez-Valentin
• Pawan Kapur