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Serial Input and Output

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Typical baud-rate values are 1200bps, 2400bps, 4800bps,9600bps and 19200bps. ... This clock signal comes from baud-rate generator (MC14411 or MC145411) ... – PowerPoint PPT presentation

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Title: Serial Input and Output


1
Serial Input and Output
2
  • ASYNCHROUS COMMUNICATIONS INTERFACE ADAPTER (ACIA)

3
Lecture Outline
1. Data communication
2. ACIA 6850
3. EIA-232
4. Programming and interface
4
ACIA LEARNING OBJECTIVES
  • After completing this course, you should be
  • able to
  • Make money?????
  • Teach other people about microprocessor
  • Design your own system by using ACIA with serial
    link to pc
  • Write a program to configure the ACIA
  • List the internal registers of the ACIA and state
    their functions
  • Or get extra tensions

5
ACIA
  • ACIA is a special chip that provides the data
    formatting and control to interface serial
    asynchronous data communication infornation to
    bus organized systems.
  • Its allows two or more microcontroller to
    interface together via 3 wire with serially
    transmitted or received
  • Normally used as modem peripheral

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  • The 6805 is an adaptor which provides controlled
    connection to and from the 6802 and peripherals
    that receive and receive data.
  • The 8-bit parallel data from the microprocessor
    is stored in a data register within the ACIA, it
    is formatted then outputted one bit (bit by bit)
    at a time to serial port.
  • The speed at which bits are sent, the number of
    bits persecond is called BAUD RATE. (units bps)
  • Typical baud-rate values are 1200bps, 2400bps,
    4800bps,9600bps and 19200bps.
  • 1 start bit-the signal line is normally high so
    the beginning of character is indicated by a
    start bit going low.

8
  • 7 or 8 bits data-normally set to 7 bits (D0-D6)
    for ASCII characters
  • 1 Parity bit-optional if transmit 7 bits of data.
    Used for error detection
  • 2 stop bits-the end of character is indicated by
    2 stop bits, both high states.
  • Two type of parity bit-even and odd.
  • If even parity bit is used, this bits will set to
    0 or 1 to make the sum of bits D0 to D7 an even
    number. Errors during transmission will indicated
    by a logic 1 in bit 6 of ACIA status register at
    receive side.

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REGISTERS OF THR ACI
  • At the bus interface, the ACIA appears as two
    addressable memory locations. Internally, there
    are 4 registers, two deal with data and two, with
    status and control.
  • Two read-only registers (status and Receive Data
    registers).
  • Two write-only registers (Control and Transmits
    Data registers)
  • Receive Data and Transmit Data registers used
    same address.
  • Status and Control registers also used same
    address.

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MASTER RESET
  • Done automatically after power-up to ensure the
    reset condition and prepare for programming the
    ACIA functional configuration when the
    communications channel is required.
  • For interfacing with MODEM, three signal, which
    permit handshake facility are provided

13
  • CTS-clear to send
  • DCD-data carrier detect
  • RTS-ready to send
  • When a MODEM is not used, CTS and DCD
  • will connect to logic LOW. RTS can be left
  • no connection.

14
  • The ACIA is memory-mapped using CS0, CS1, CS2 and
    RS it appears as only 2 addressable memory
    locations.
  • The register select pin together with R/W is used
    to select each register.
  • Transmit Data Register (TDR)
  • The byte of data to be transmitted is written to
    the TDR by microprocessor. It is transferred to
    the transmit shift register, if its is empty, the
    byte is then shifted out serially.
  • Data will written into TDR during negative
    transition of the enable, pin E when the ACIA has
    been addressed with RS high and R/W low.

15
  • Receive Data Register (RDR)
  • Information from external devices enters the ACIA
    serially via the receive shift register, which
    strips off the start and Stop bits and sends the
    byte in a parallel transfer to the RDR.
  • The processor must read the RDR while the second
    byte is being received.
  • Control Register (CR)
  • This register controls the format of both the
    transmitted and received data.
  • Status Register (SR)
  • Monitors the progress of data transmission and
    reception and sends it to the microprocessor.

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PROGRAMMING THE ACIA
  • Programming is accomplished by sending an 8 bit
    number out to the ACIA control register (CR).
  • Bit CR0 and CR1 select the appropriate baud-rate
    multiplier and also can reset the chip.
  • Example if the input clock frequency is
    19,200Hz, divide by 1 would cause operation at
    19,200 bps. If divide by 16 would cause operation
    at 1,200 bps.
  • This clock signal comes from baud-rate generator
    (MC14411 or MC145411).
  • The ACIA is reset to clear any error indications
    in the status register (SR).

18
  • Bit CR2, CR3, CR4 determine the format of the
    character that will be transmitted and received
    by the ACIA.
  • Example If all 3 bits are programmed as zeros, 7
    data bits with even parity and 2 stop bits are
    transmitted and received.
  • CR5 and CR6 control the transmitter interrupt and
    RTS pin and determine whether or not a break
    character is transmitted. Normally used for
    MODEM.
  • CR7, enable IRQ pin. IRQ0 occurs for a received
    byte of data, an overrun error, or positive
    transition on the DCD pin.

19
  • Status register (SR) is read by selecting the
    device and placing a logic zero on the RS pin.
  • This SR indicates error conditions, the
    conditions of some of the MODEM control pins, and
    the general operating condition of the ACIA.
  • RDRF indicates that data is available for the
    microprocessor, which must read or removed it
    before the next data/character is received into
    RDR. If not, the OR bit will set to one.

20
  • RDRF is logic high when full and become empty (0)
    after read operation.
  • TDRE, acknowledge to the microprocessor to load
    character/data into TDR when empty (TDRE1). The
    write command cause TDRE0. TDRE automatically
    set to one when the ACIA complete transmit the
    contents of TDR.
  • IRQ status bit indicates that the input buffer
    (RDR) is full. CR7 at control register (CR) must
    set to one if we used external interrupt pin
    (IRQ).

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HOW TO ACCES ACIA?
  • Before we start writing a program to acces
  • the ACIA device, the following procedure
  • must be followed.
  • Choose the Baud rate clock at baud rate generator
    by selecting the RSA and RSB according to the
    speed what we want to used.
  • Initialized the ACIA by putting 03 hex into
    conrol register
  • Choose the type of transmission by stored control
    word into control register. The counter divide
    inside control register (CR0 and CR1) must select
    according to the value has been choose at baud
    rate generator (RSA and RSB)

24
HOW TO INTERFACE AN ACIA WITH IBM PC?
  • The RS-232C interface standard is almost
    universally used for the interconnection of
    terminal equipment such printer, keyboard, MODEM,
    tape recorder, CRT stcs. That receives and
    tranmits serial asynchronous data.
  • The standard specifies the pin connections and
    connector to be employed.
  • For RS-2332C, there is two types of connector can
    be used
  • DB-25 male/female (25pins)
  • DB-9 male/female (9 pins)

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