Layout for Inverter Using 2NMOS with saturated Load

1
Four-to-One Analog Multiplexer in Time-
Domain Research Experience for
Undergraduates Summer 2002Project
PresentationJuly 19, 2002

• Apurva Patel
• Tara Terry
• Advisor Professor Hoda S. Abdel-Aty-Zohdy

2
Presentation Contents

• Project Overview
• Statement and Need of the Problem
• Our Part in the project
• Approach to solve the problem Design
• Integrated Circuit Layout And Simulation Results
• Applications
• Comparison with other TDM Techniques
• Conclusions

3
The Need for Analog Multiplexing
-Image Processing as with VIGILANTE -Voice
Signal Processing -Signal Real-Time Processing of
Sensor Measurements -Chemical
Sensors -Pressure sensors -Temperature
Sensors -Accelerometers -Bio-Medical
Instrumentation..etc, etc
4
The Entire Project
5
Our Part in the Entire Project

• To do pre-processing on the signal coming from
  the sensors
• To guide the signals coming from the
  sensors to the appropriate signal processing
  units.
• To build a Time-Domain Multiplexing system that
  multiplexes the incoming signals.
• To build the system by applying simple concepts
  of micro-electronic circuits.

6
Problem and Purpose
Problem We need to take analog signals coming
from sensors and send those signals out, with no
distortion, to the processing units. Purpose
Multiplexing of the signals is needed to minimize
the complexity of the circuit and to be cost
effective, with the idea of building the entire
electronic nose on a single chip.
7
Basics of the Circuit

• Inverter
• Vin 1 Vout 0
• Two Inverters cascaded to form a Buffer
• Buffer Transmission Gate One Input Module

Vout 1
Vin 1
Buffer
Vin 1
Vout 1 depends whether the switch is closed
8
Basic Model of the Circuit

• Putting four such modules gives 4 to 1 Mux

Vin1
Vin2
Vin3
Data out
Vin4
9
Three Types of Inverter Circuit Model were tested
for building the buffer
Vdd
Vdd
Vdd
Resistor
Vout
Vout
Vout
Vin
Vin
To Vdd
Vin
NMOS with a saturated NMOS Load (the one we
selected) Figure-2
CMOS Inverter (Widely Used as a Digital
Inverter) Figure-3
NMOS with a Resistor Load Figure-1
10
Approach used to select the best Inverter circuit
Model
Do simulations on the circuit using Spice
Observe the Transfer Characteristics for the
following characteristics
Good Linear Range which should at least cover
48-60 of the Input Range
Slope of the Linear Range which should be from
0.6 1.2 V/V
11
Results for choosing the Inverter design
12
Simulation results showing the Transfer
Characteristics for the Three Inverter Circuit
Models
For NMOSResistor (figure-2) Inverter, slope
-3.3
For CMOS Inverter (figure-1) Slope is very high
-39.5
The input linear range it covers is much less
(from 1.0-2.0)
For 2-NMOS Inverter (figure-3), slope -0.8 This
circuit matches our criteria
13
Things to be done after selecting the Inverter
Circuit Model

• Prepare and simulate the layout of the inverter ?
  buffer ? 4 to 1 mux.
• Use MicroWind as the software tool to prepare and
  simulate the layouts.
• Choose the best CMOS technology (layout
  specifications describing the size and
  performance) for preparing the layout.

14
Layout for Inverter Using 2-NMOS with Saturated
Load
Saturated Load
Vdd
Vdd
vout
Vout
Vout
Vin
Ground
Vin
Unsaturated Driver
15
Layout for Buffer by cascading two Inverter
Circuits
Vdd
Vdd
Vout
Vout
Vin1
Vin2
Vin2
Vin1
16
Layout of a Buffer with a Transmission Gate
Transmission Gate
nEnable
Vdd
Vout
Data Out
Vout
Vin
Data out
Enable
Vin
Buffer
17
Layout for 4 to 1 Multiplexer obtained by
cascading Four Buffer and Transmission Gates
Vout1
Vin1
Vin1
Vout2
Vin2
Vin2
DATA OUT
Vin3
DATA OUT
Vout3
Vin4
Vin3
Vout4
Vin4
18
Layout Specifications and CMOS Technology Used

• Simulations and Layout for three types of CMOS
  Technology were carried out
• 1.2 µm Technology Gives W6.0 µm L1.2 µm for
  NMOS Transistor
• 0.35 µm Technology Gives W2.0 µm L0.4 µm
  for NMOS Transistor(Pentium-4 is
  made up of 0.35 µm Technology)
• 0.12 µm Technology Gives W0.60 µm L0.12 µm
  for NMOS Transistor (it is
  theoretically based, has not been
  tried)

19
Results for Three CMOS Technologies
The Vdd used for each case was 3.3 volts.
20
Simulation Results
For 1.2 ?m CMOS Technology
Transfer Characteristics for the Buffer
Linear Range of Operation (0.6 2.0) V
21
Simulation Results..
For 1.2 ?m CMOS Technology
Timing Diagram showing the Maximum Peak to Peak
Input Possible and Delay
Time Delay
No distortion Vinp-p 1.6 volts
1.3 ns
22
Simulation Results..
For 1.2 ?m CMOS Technology
Pulse Timing Diagram showing Maximum Frequency
Limitations (which is 0.193 Ghz)
Input Square Pulse with 0.25 Ghz frequency
Distorted Output showing maximum frequency
limitations
23
Simulation Results..
For 0.35 ?m CMOS Technology
Transfer Characteristics for the Buffer
Linear Range of operation (0.6 2.3) V With a
slope of 0.8 V/V
24
Simulation Results..
For 0.35 ?m CMOS Technology
Timing Diagram showing the Maximum Peak to Peak
Input Possible and Delay
Vinp-p 1.6 volt
Time Delay
0.4 ns
Undistorted Vout signal
25
Simulation Results..
For 0.35 ?m CMOS Technology
Pulse Timing Diagram showing Maximum Frequency
Limitations (which is 4-6 Ghz)
Input Square Pulse signal of 4.10 Ghz frequency
Distorted output signal showing frequency
limitations
26
Simulation Results..
For 0.12 ?m CMOS Technology
Transfer Characteristics for the Buffer
Linear Range (0.6-2.4 volts) Slope 0.8 V/V
27
Simulation Results..
For 0.12 ?m CMOS Technology
Timing Diagram showing the Maximum Peak to Peak
Input Possible and Delay
Time Delay is only 12 ps
Vinp-p 2.0 v
28
Simulation Results..
For 0.12 ?m CMOS Technology
Pulse Timing Diagram showing Maximum Frequency
Limitations (which is 20.8 Ghz for a square
pulse). However, the delay of 12 ps can be seen
easily when a sine wave having a frequency of 128
Ghz is applied to the input.
The delay can be seen easily, (the input has a
frequency of 100-128 Ghz)
29
Result Summary revisited
30
Final simulation result showing the working of
the 4 to1 mux
Vin1 goes to output
Vin2 goes to output
Vin3 goes to output
Vin4 goes to output
31
Experimental vs. Theoretical Results
32
Applications

• Biochemical Sensor Detection
• The ongoing project of Gas detection
  (E-nose) done at Wright/Patterson Air Force Base,
  Dayton, Ohio.
• Time Domain Multiplexing of serial Fiber Bragg
  Grating Sensor Arrays.
• Requires Multiplexing of the analog
  signals coming from sensors (in the form of Bragg
  Gratings), so that only a single (at most few)
  signal transmission channel(s) and only one
  signal processing center are required.
  
  The Bragg Grating Sensor Array
  project is currently carried out at the
  University of Toronto in Toronto, Canada.
  

33
ApplicationsContd...

• Image Processing and Face Recognition
• VIGILANTE A sugar cube sized brain that
  does tera-operations/sec
  and capable of performing image
  convolution.
• The cube is analog
  but the rest of the signal processing
  is digital and involves 64
  A/D converters in the first
  phase increasing the cost and
  slowing the process.
• However a crucial improvement in
  the performance was made by
  including a 2 to1 Mux.

34
                                                
                                                  
                                                  
                                                  
                  
35
VIGILANTE Daughter Board using 2-1 Analog MUX
Daughter board 2 is 8x9 in2 with 16-layer PCB
and only 32 ADCs.
36
ApplicationsContd
The image processing and face recognition project
is currently being researched in conjunction with
VIGILANTE the Viewing Imager/Gimbaled
Instrumentation Laboratory and Analog Neural
Three-Dimensional Experiment Program at
Wright/Patterson Air-Force Base, Dayton, Ohio
with Dr. H. S. Abdel-Aty-Zohdy

• Commercial Application 8 to 1 Mux and dual 4
  to 1 Mux are commercially
  produced by a company named Maxim
  in Dallas.
• No
  Circuit specifications are available
  

37
Analog Time Domain Multiplexing (TDM)

• What is TDM ?
• TDM is an analog multiplexing concept in time
  domain which is applied in communications.
• Most often seen in long range communication.

Router (logical algorithms) N X N Switch Matrix
Multiplexer Modems
Demultiplexer Modems
Data Transmitting centers
Data Receiving Center
TDM Circuit
38
Why other TDM circuits are Not Useful for E-Nose
Application
Other TDM circuits are more useful for large
number of inputs and multi-agents that are
unlocalized (such as cell phones) but a 4-1
multiplexer is more effective when the receiving
station and processing station are on the same
chip.
Data Transmission
Sensor Array
41 Analog Multiplexer Array
Bio-Inspired Intelligent, Cognitive, Decision-
Making circuits
n/4
n
Entire Circuit on a single chip
39
Analog Multiplexing In Frequency Domain

• Analog Multiplexing In Frequency Domain Requires
• Distinct carrier frequencies to be generated and
  attached to each incoming signal
• Carrier frequencies must be chosen adjacent so
  that there is no overlap
• Separated by pre-determined intervals based on
  signal bandwidth
• Time Domain doesnt require identification codes
  and the time duration is fixed by a clock pulse.

40
Advantage of 41 Analog Multiplexer Over other
TDM Circuits

• Small size 4 buffers 4 transmission gate
  -vs-
  
  TDM circuit (more than 32 transistors)
  
• Hardware and cost effective.
• Time Effective Time Delay is 1.3 ns for 1.2?m
  CMOS process
  
  -vs-
  
  Time Delay that depends on total
  number of input, outputs, and switch
  size matrix in TDM circuits.

41
What Is Left To Do?

• FOLLOW UP WORK
• Design Integration in an Integrated Circuit PAD
  FRAME
• Create Electronic File for Submission to be
  processed in a
• IC chip
• Testing, Evaluation and Validation of the
  prototype
• Work for OTHERS
• Integrate the MUX with sensors in a
  System-on-a-Chip
• IC design
• APPLICATIONS Implementation

42
List of References

• Cyril S. Gibbons. Time Domain Multiplexing of
  Serial Fiber Bragg Grating Sensor Arrays.
  Invention that has U.S. and Canadian-filed patent
  applications.
• John Pike. Communication Networks.
  Introduction to Naval Weapons Engineering.
  
  http//www.fas.org/man/dod-101/navy/docs/es310/Co
  mNets.htm
• Suraphol Udomkesmalee, Curtis Padgett, David Zhu,
  Gerald Lung, Ayanna Howard, David Ludwig, and
  Maj. George Moretti, Tera-ops Processing for ATR.
  San Diego, CA, July 2000. AIAA/BMDO Technology
  Conference. 9th Annual Conference.
• Kwan L. Yeung. Efficient Time Slot Assignment
  Algorigthms for TDM Heirarchical and
  Nonhierarchical Switching Systems. IEEE
  Transactions On Communications, 49(2)351-359,
  February 20001.

43
List of References Contd..

• Dr. Hoda S. Abdel-Aty-Zohdy, Dr. Robert L. Ewing,
  Dr. Misoon C. Mah, and Dr. Lihyeh Liou.
  Integrated Circuits and Systems for Solving
  Biochemical Sensor Development and Detection
  Problems. 2002.
• Adel S. Sedra and Kenneth C. Smith.
  Microelectronic Circuits. Oxford University
  Press, New York, fourth edition, 1998.

44
Conclusion Technical

• The 4 to1 Multiplexer is small in size and
  operates in the linear range of its transfer
  characteristics.
• The 4 to 1 Multiplexer gives a Linear Range
  48-51 of the total Input Range.
• Less power consumption.
• It can be implemented using 0.35um Technology.
• Time Delay of only 0.5-0.6 ns for 0.35um
  Technology
• Maximum Frequency Limitations for Input Signal is
  4-6 GHz for 0.35um Technology.

45
Things We Learned From The Project

• Doing Simulations Using Spice.
• Creating and simulating Layouts using Microwind.
• Understanding how to look for Time-Delays in
  simulation results and calculating frequency
  limitations.
• Different techniques of multiplexing.
• Knowing how changes in Parameters affects the
  performance of the circuit.

46
ACKNOWLEDGMENTS
Our Special Thanks to

• Professor Ishwar Sethi

• Professor Fatma Mili

• Professor Hoda S. Abdel-Aty-Zohdy

• Dr. Daniela Stan

• MSDL Lab Partners Dipti, Deepak and Fatma

• REU Group Members Priscilla, Nick, Rishi,
  Aiyesha and Amanda

47
WPAFB VISIT(Wright Patterson Air Force Base)

• We Also Would Like to Recognize and Thank
• Dr. Robert L. Ewing
• Dr. Misoon Mah
• Lt. Tony Chang
• Professor Frank Scarpino

48
IEEE MWSCAS Conference IEEE International Midwest
Symposium on Circuits and Systems
TITLE Analog Multiplexing in Time Domain for
Biochemical Measurement Processing AUTHORS
Apurva Patel, Tara Terry and
Professor Hoda S. Abdel-Aty-Zohdy PUBLIC DATE
August 4-7, 2002 LOCATION Oklahoma State
University, Tulsa, Oklahoma ABSTRACT Can Be
Found At http//www.oakland.edu/aapatel/OurResea
rch.htm