Approaching the Physical Limits of Computing

1
Approaching the Physical Limits of Computing

• Invited talk, presented at ISMVL 200535th Intl
  Symp. on Multiple-Valued Logic(Sponsor IEEE
  Computer Society)
• Friday, May 20, 2005

2
Abstract of Talk

• Fundamental physics limits the performance of
  conventional computing technologies.
• The energy efficiency of conventional machines
  will be forced to level off in roughly the next
  10-20 years.
• Practical computer performance will then plateau
  as well.
• However, all of the proven limits to computer
  energy efficiency can, in principle, be
  circumvented
• but only if computing undergoes a radical
  paradigm shift.
• The essential new paradigm Reversible computing.
• It involves reusing energy to improve energy
  efficiency.
• However, doing this well tightly constrains
  computer design at all levels from devices
  through logic, architectures, and algorithms.
• In this talk, I review the stringent physical and
  logical requirements that must be met,
• if we wish to break through the near-term
  barriers,
• and approach the true physical limits of
  computing.

3
Moores Law and Performance

• Gordon Moore, 1975
• Devices per IC can bedoubled every 18 months
• Borne out by history!
• Some fortuitous corollaries
• Every 3 years Devices ½ as long
• Every 1.5 years ½ as much stored energy per
  bit!
• It is that that has enabled us to throw away bits
  (and their energies) 2 more frequently every
  1.5 years, at reasonable power levels!
• And thereby double processor performance 2 every
  1.5 years!
• Increased energy efficiency of computation is a
  prerequisite for improved raw performance!
• Given realistic levels of total power consumption.

Devices per IC
Year of Introduction
4
Efficiency in General, and Energy Efficiency

• The efficiency ? of any process is ? P/C
• Where P Amount of some valued product produced
• and C Amount of some costly resources consumed
• In energy efficiency ?e, the cost C measures
  energy.
• We can talk about the energy efficiency of
• A heat engine ?he W/Q, where
• W work energy output, Q heat energy input
• An energy recovering process ?er Eend/Estart,
  where
• Eend available energy at end of process,
• Estart energy input at start of process
• A computer ?ec Nops/Econs, where
• Nops useful operations performed
• Econs free-energy consumed

5
Trend of Minimum Transistor Switching Energy
Based on ITRS 97-03 roadmaps
fJ
Node numbers(nm DRAM hp)
Practical limit for CMOS?
aJ
CV2/2 gate energy, Joules
Naïve linear extrapolation
zJ
6
Some Lower Bounds on Energy Dissipation

• In todays 90 nm VLSI technology, for minimal
  operations (e.g., conventional switching of a
  minimum-sized transistor)
• Ediss,op is on the order of 1 fJ (femtojoule) ?
  ?ec ? 1015 ops/sec/watt.
• Will be a bit better in coming technologies (65
  nm, maybe 45 nm)
• But, conventional digital technologies are
  subject to several lower bounds on their energy
  dissipation Ediss,op for digital transitions
  (logic / storage / communication operations),
• And thus, corresponding upper bounds on their
  energy efficiency.
• Some of the known bounds include
• Leakage-based limit for high-performance
  field-effect transistors
• Maybe roughly 5 aJ (attojoules) ? ?ec ? 21017
  operations/sec./watt
• Reliability-based limit for all
  non-energy-recovering technologies
• On the order of 1 eV (electron-volt) ? ?ec ?
  61018 ops./sec/watt
• von Neumann-Landauer (VNL) bound for all
  irreversible technologies
• Exactly kT ln 2 18 meV ? ?ec ? 3.51020
  ops/sec/watt
• For systems whose waste heat ultimately winds up
  in Earths atmosphere,
• i.e., at temperature T Troom 300 K.

7
Reliability Bound on Logic Signal Energies

• Let Esig denote the logic signal energy,
• The energy involved (transferred, manipulated) in
  the process of storing, transmitting, or
  transforming a bits worth of digital
  information.
• But note that involved does not necessarily
  mean dissipated!
• As a result of fundamental thermodynamic
  considerations, it is required that Esig ? kBTsig
  ln r (with quantum corrections that are small for
  large r)
• Where kB is Boltzmanns constant, 1.3810-12 J/K
• and Tsig is the temperature in the degrees of
  freedom carrying the signal
• and r is the reliability factor, i.e., the
  improbability of error, 1/perr.
• In non-energy-recovering logic technologies
  (totally dominant today)
• Basically all of the signal energy is dissipated
  to heat on each operation.
• And often additional energy (e.g., short-circuit
  power) as well.
• In this case, minimum sustainable dissipation is
  Ediss,op ? kBTenv ln r,
• Where Tenv is now the temperature of the
  waste-heat reservoir (environment)
• Averages around 300 K (room temperature) in
  Earths atmosphere
• For a decent r of e.g. 21017, this energy is on
  the order 40 kT 1 eV.
• Therefore, if we want energy efficiency ?ec gt 1
  op/eV, we must recover some of the signal energy
  for later reuse.
• Rather than dissipating it all to heat with each
  manipulation of the signal.

8
The von Neumann-Landauer (VNL) Principle

• First alluded to by John von Neumann in 1949.
• Developed explicitly by Rolf Landauer of IBM in
  1961.
• The principle is a rigorous theorem of physics!
• It follows from the reversibility of fundamental
  dynamics.
• A correct statement of the principle is the
  following
• Any process that loses or obliviously erases 1
  bit of known (correlated) information increases
  total entropy by at least ?S 1 bit kB ln
  2,
• and thus implies the eventual dissipation at
  least Ediss kBTenv ln 2 of free energy to
  the environment as waste heat.
• where kB log e 1.3810-23 J/K is Boltzmanns
  constant
• and Tenv temperature of the waste-heat
  reservoir (environment)
• Not less than about room temperature, or 300 K
  for earthbound computers. ? implies Ediss 18
  meV.

9
Definition of Reversibility

• What does it mean for a dynamical system (either
  continuous or discrete) to be (time-) reversible?
• Let x(t) denote the state of the system at time
  t.
• The universe, or any closed system of interest
  (e.g. a computer).
• Let Ft?u(x) be the transition relation operating
  between a given two times t and u i.e., x(u)
  Ft?ux(t).
• Determined by the systems dynamics (laws of
  physics, or a FSM).
• Then the system is called dynamically
  reversible iff Ft?u is a one-to-one function,
  for any times (t, u) where u gt t.
• That is, ? t gtu ? x1?x2 Ft?u(x1) Ft?u(x2).
• That is, no two distinct states would ever go to
  the same state over the course of a given time
  interval.
• The definition implies determinism, if we also
  allow u lt t.
• A reversible system is deterministic in the
  reverse time direction.

10
Types of Dynamics

• Nondeterministic,irreversible
• Deterministic,irreversible

• Nondeterministic,reversible
• Deterministic,reversible

11
Physics is Reversible!

• All of the successful models of fundamental
  physics are expressible in the Hamiltonian
  formalism.
• Including Classical mechanics, quantum
  mechanics, special and general relativity,
  quantum field theories.
• The latter two (GR QFT) are backed up by
  enormous, overwhelming mountains of evidence
  confirming their predictions!
• 11 decimal places of precision so far! And, no
  contradicting evidence.
• In Hamiltonian systems, the dynamical state x(t)
  obeys a differential equation thats first-order
  in time, dx/dt g(x) (where g is some
  function)
• This immediately implies determinism of the
  dynamics.
• And, since the time differential dt can be taken
  to be negative, the formalism also implies
  reversibility!
• Thus, dynamical reversibility is one of the most
  firmly-established, fundamental, inviolable facts
  of physics!

12
Illustration of VNL Principle

• Either digital state is initially encoded by any
  of N possible physical microstates
• Illustrated as 4 in this simple example (the real
  number would usually be much larger)
• Initial entropy S logmicrostates log 4 2
  bits.
• Reversibility of physics ensures bit erasure
  operation cant possibly merge two microstates,
  so it must double the possible microstates in the
  digital state!
• Entropy S logmicrostates increases by log 2
  1 bit (log e)(ln 2) kB ln 2.
• To prevent entropy from accumulating locally, it
  must be expelled into the environment.

Microstates representinglogical 0
Microstates representinglogical 1
Entropy S log 4 2 bits
Entropy S' log 8 3 bits
Entropy S log 4 2 bits
?S S' - S 3 bits - 2 bits 1 bit
13
Reversible Computing

• The basic idea is simply this
• Dont erase information when performing logic /
  storage / communication operations!
• Instead, just reversibly (invertibly) transform
  it in place!
• When reversible digital operations are
  implemented using well-designed energy-recovering
  circuitry,
• This can result in local energy dissipation
  Ediss ltlt Esig,
• this has already been empirically demonstrated by
  many groups.
• and even total energy dissipation Ediss ltlt kT ln
  2!
• This is easily shown in theory simulations,
• but we are not yet to the point of demonstrating
  such low levels of total dissipation empirically
  in a physical experiment.
• Achieving this goal requires very careful design,
  
• and verifying it requires very sensitive
  measurement equipment.

14
How Reversible Logic Avoids the von
Neumann-Landauer Bound

• We arrange our logical manipulations to never
  attempt to merge two distinct digital states,
• but only to reversiblytransform them fromone
  state to another!
• E.g., illustrated is a reversible operationcCLR
  (controlled CLR)
• It and its inverse cSETenable arbitrary logic!

logic 00
logic 01
logic 10
logic 11
15
A Few Highlights Of Reversible Computing History

• Charles Bennett _at_ IBM, 1973-1989
• Reversible Turing machines emulation algorithms
• Can emulate irreversible machines on reversible
  architectures.
• But, the emulation introduces some inefficiencies
• Models of chemical Brownian-motion physical
  realizations.
• Fredkin and Toffolis group _at_ MIT, late
  1970s/early 1980s
• Reversible logic gates and networks (space/time
  diagrams)
• Ballistic and adiabatic circuit implementation
  proposals
• Groups _at_ Caltech, ISI, Amherst, Xerox, MIT,
  85-95
• Concepts for implementations of adiabatic
  circuits in VLSI tech.
• Small explosion of adiabatic circuit literature
  since then!
• Mid 1990s-today
• Better understanding of overheads, tradeoffs,
  asymptotic scaling
• A few groups begin development of post-CMOS
  implementations
• Most notably, the Quantum-dot Cellular Automata
  group at Notre Dame

16
Caveat 1

• Technically, to avoid the VNL bound doesnt
  actually require that the digital operation must
  be reversible at the level of the logical states
• It can be logically irreversible if the
  information in the digital state is already
  entropy!
• In the below example, the non-digital entropy
  doesnt change, because the operation is also
  nondeterministic (N to N), and the transition
  relation between logical states has semi-detailed
  balance, so the entropy in the digital state
  remains constant.
• However, such operations just re-randomize bits
  that are already random!
• Its not clear if this kind of operation is
  computationally useful.

0
0
Digital bit with unknown value
1
1
Physical dynamics whose precisedetails may be
uncertain
17
Caveat 2

• Operations that are logically N-to-1 can be used,
  if there are sufficient compensating 1-to-N
  (nondeterministic) logical operations.
• All that is really required is that the logical
  dynamics be 1-to-1 in the long-term average.
• Thus, its possible to thermally generate random
  bits and discard them later when we are through
  with them.
• While maintaining overall thermodynamic
  reversibility.
• This ability is useful for probabilistic
  (randomized) algorithms.

logic 0
logic 1
18
Reversibility and Reliability

• A widespread myth Future low-level digital
  devices will necessarily be highly unreliable.
• This comes from a flawed line of reasoning
• Faster ? more energy efficient ? lower bit
  energies ? high rate of bit errors from thermal
  noise
• However, this scaling strategy doesnt work,
  because
• High rate of thermal errors ? high power
  dissipation from error correction ? less energy
  efficient ? ultimately slower!
• But in contrast, using reversible computing, we
  can achieve arbitrarily high energy efficiency
  while also maintaining arbitrarily high
  reliability!
• The key is to keep bit energies reasonably high!
• While recovering most of the bit energy

19
Minimizing Energy Dissipation Due to Thermal
Errors

• Let perr 1/r be the bit-error probability per
  operation.
• Where r quantifies the reliability level.
• And pok 1 - perr is the probability the bit is
  correct
• The necessary entropy increase ?S per op due to
  error occurrence is given by the (binary) Shannon
  entropy of the bit-value after the operation
• H(perr) perr log perr-1 pok log pok-1.
• For r gtgt 1 (i.e., as r ? 8), this increase
  approaches 0
• ?S H(perr) perr log perr-1 (log r)/r ? 0
• Thus, the required energy dissipation per op also
  approaches 0
• Ediss T?S (kT ln r)/r ? 0
• Could get the same result by assuming the signal
  energy Esig kT ln r required for reliability
  level r is dissipated each time an error occurs
• Ediss perrEsig perr(kT ln r) (kT ln r)/r
  ? 0 as r ? 8.
• Further, note that as r ? 8, the required signal
  energy grows only very slowly
• Specifically, only logarithmically in the
  reliability, i.e., Esig T(log r).

20
Device-Level Requirements for Reversible Computing

• A good reversible device technology should have
• Low manufacturing cost d per device
• Important for good overall (system-level)
  cost-efficiency
• Low rate of static power dissipation Pleak due to
  energy leakage.
• Required for energy-efficient storage especially
  (but also in logic)
• Low energy coefficient cE Ediss/f (energy
  dissipated per operation, per unit transition
  frequency) for adiabatic transitions.
• Implies we can achieve a high operating frequency
  (and thus good cost-performance) at a given level
  of energy efficiency.
• High maximum available transition frequency fmax.
• Important for those applications in which the
  latency of serial threads of computation
  dominates total cost
• Important For system-level energy efficiency,
  Pleak and cE must be taken as effective global
  values measuring the implied amount of energy
  emitted into the outside environment at
  temperature Tenv.
• With an ideal (Carnot) refrigerator, Pleak
  StTenv and cE cSTenv,
• Where St the static rate of leakage entropy
  generation per unit time,
• and cS Sgen/f adiabatic entropy coefficient, or
  entropy generated per unit transition frequency.

21
Early Chemical Implementations

• How to physically implement reversible logic?
• Bennetts original inspiration DNA
  polymerization!
• Reversible copying of a DNA strand
• Molecular basis of cell division / organism
  reproduction
• This (and all) chemical reactions are reversible
• Direction (forward vs. backward) reaction rate
  depends on relative concentrations of reagent and
  product species ? affect free energy
• Energy dissipated per step turns out to be
  proportional to speed.
• Implies process is characterized by an
  energy-time constant.
• I call this the energy coefficient cEt
  Ediss,optop Ediss,op/fop.
• For DNA, typical figures are 40 kT 1eV _at_ 1,000
  bp/s
• Thus, the energy coefficient cE is about 1
  eV/kHz.
• Can we achieve better energy coefficients?
• Yes, in fact, we had already beat DNAs cE in
  reversible CMOS VLSI technology available circa
  1995!

22
Energy Entropy Coefficients in Electronics
Q
R

• For a transition involving the adiabatic transfer
  of an amount Q of charge along a path with
  resistance R
• The raw (local) energy coefficient is given by
  cEt Edisst Pdisst2 IVt2 I2Rt2 Q2R.
• Where V is the voltage drop along the path.
• The entropy coefficient cSt Q2R/Tpath.
• where Tpath is the local thermodynamic
  temperature in the path.
• The effective (global) energy coefficient is
  cEt,eff Q2R(Tenv/Tpath).
• We pay a penalty for low-T operation!

23
Example of Electronic cEt

• In a fairly recent (180 nm) CMOS VLSI technology
• Energy stored per min. sized transistor gate 1
  fJ _at_ 2V
• Corresponds to charge per gate of Q 1 fC
  6,000 electrons
• Resistance per turned-on min-sized nFET of 14 k?
• Order of the quantum resistance R R0 1/G0
  h/2q2 12.9 k?
• Ideal energy coefficient for a single-gate
  transition 1.410-26 J/Hz
• Or in more convenient units, 80 eV/GHz 0.08
  eV/MHz!
• with some expected overheads for a simple test
  circuit, calculated energy coefficient comes out
  to about 8 higher, or 10-25 Js
• Or 600 eV/GHz 0.6 eV/MHz.
• Detailed Cadence simulations gave us, per
  transistor
• _at_ 1 GHz P 20 µW, E 20 fJ 1.2 keV, so Ec
  1.2 eV/MHz
• _at_ 1 MHz P 0.35 pW, E 3.5 aJ 2.2 eV, so Ec
  2.1 eV/MHz

24
Cadence Simulation Results

• Graph shows power dissipation vs. frequency
• in a shift register.
• At moderate frequencies (1 MHz),
• Reversible uses lt 1/100th the power of
  irreversible!
• At ultra-low power (1 pW/transistor)
• Reversible is 100 faster than irreversible!
• Minimum energy dissipation lt 1 eV!
• 500 lower than best irreversible!
• 500 higher computational energy efficiency!
• Energy transferred is still 10 fJ (100 keV)
• So, energy recovery efficiency is 99.999!
• Not including losses in power supply

2LAL Two-level adiabatic logic
1 nJ
100 pJ
Standard CMOS
10 aJ
10 pJ
1 aJ
1 pJ
Energy dissipated per nFET per cycle
1 eV
100 fJ
2V
100 zJ
2LAL 1.8-2V
1V
10 fJ
10 zJ
0.5V
0.25V
kT ln 2
1 fJ
1 zJ
100 aJ
100 yJ
25
A Useful Two-Bit PrimitiveControlled-SET or
cSET(a,b)

• Semantics If a1, then set b1.
• Conditionally reversible, if the special
  precondition ab0 is met.
• Note its 1-to-1 on the subset of states used
• Sufficient to avoid Landauers principle!
• We can implement cSET in dual-rail CMOS with a
  pair of transmission gates
• Each needs just 2 transistors,
• plus one controlling drive signal
• This 2-bit semi-reversible operation its
  inverse cCLR are universal for reversible (and
  irreversible) logic!
• If we compose them in special ways.
• And include latches for sequential logic.

a b a b
0 0 0 0
0 1 0 1
1 0 1 1
drive
(0?1)
a
switch(T-gate)
b
b
a
26
Reversible OR (rOR) from cSET

• Semantics rOR(a,b) if ab, c1.
• Set c1, on the condition that either a or b is
  1.
• Reversible under precondition that initially ab
  ? c.
• Two parallel cSETs simultaneouslydriving a
  shared output lineimplement the rOR operation!
• This type of gate composition was not
  traditionally considered.
• Similarly one can do rAND, and
  reversibleversions of all operations.
• Logic synthesis with theseis extremely
  straightforward

Hardware diagram
a
c
b
Spacetime diagram
a
a
a OR b
0
c
c
b
b
27
CMOS Gate Implementing rLatch / rUnLatch

• Symmetric Reversible Latch

Implementation
Icon
Spacetime Diagram
crLatch
crUnLatch
connect
in
mem
in
2
mem
in
or
connect
(in)
mem
in
mem

• The hardware is just a CMOS transmission gate
  again
• This time controlled by a clock, with the data
  signal driving
• Concise, symmetric hardware icon Just a short
  orthogonal line
• Thin strapping lines denote connection in
  spacetime diagram.

28
Example Building cNOT from rlXOR

• rlXOR(a,b,c) Reversible latched XOR.
• Semantics c a?b.
• Reversible under precondition that c is initially
  clear.
• cNOT(a,b) Controlled-NOT operation.
• Semantics b a?b. (No preconditions.)
• A classic primitive operation in reversible
  quantum computing
• But, it turns out to be fairly complex to
  implement cNOT in available fully adiabatic
  hardware technologies
• Thus, its really not a very good building block
  for practical reversible hardware designs!
• Of course, we can still build it, if we really
  want to.
• Since, as I said, our gate set is universal for
  reversible logic

29
cNOT from rlXOR Hardware Diagram

• A logic block providing an in-place cNOT
  operation (a cNOT gate) can be constructed
  from 2 rlXOR gates and two latched buffers.
• The key is
• Operate some of the gates in reverse!

Reversiblelatches
A
B
X
30
T(log n)-time carry-skip adder
With this structure, we can do a2n-bit add in
2(n1) logic levels? 4(n1) reversible ticks?
n1 clock cycles. Hardwareoverhead islt 2
regularripple-carry! Spacetimeoverhead
only 2(n1) a conventionalsingle-cycleequival
ent.

• (8 bit segment shown)

3rd carry tick
2nd carry tick
4th carry tick
1st carry tick
31
32-bit Adder Simulation Results
1V CMOS
1V CMOS
0.5V CMOS
0.5V CMOS
2V 2LAL, Vsb1V
2V 2LAL, Vsb1V
(All results here are normalized to a throughput
level of 1 add/cycle)
32
Technological Challenges

• Fundamental theoretical challenges
• Find more efficient reversible algorithms
• Or, prove rigorous lower bounds on complexity
  overheads
• Study fundamental physical limits of reversible
  computing
• Implementation challenges
• Design new devices with lower energy coefficients
  cEt
• Design high-quality resonators for driving
  transitions
• Empirically demonstrate large system-level power
  savings
• Application development challenges
• Find a plausible near- to medium-term killer
  app for RC
• Something thats very valuable, and cant be done
  without it
• Build a prototype RC-based solution prototype

33
Plenty of Room forDevice Improvement
Power per device, vs. frequency

• Recall, irreversible device technology has at
  most 3-4 orders of magnitude of
  power-performance improvements remaining.
• And then, the firm kT ln 2 (VNL) limit is
  encountered.
• But, a wide variety of proposed reversible device
  technologies have been analyzed by physicists.
• With theoretical power-performance up to 10-12
  orders of magnitude better than todays CMOS!
• Ultimate limits are unclear.

.18µm CMOS
.18µm 2LAL
k(300 K) ln 2
Variousreversibledevice proposals
34
Limiting Cases of Energy/Entropy Coefficients

• Entropy/entropy coefficients in adiabatic single
  electronics
• Suppose the amount of charge moved Q q (a
  single electron)
• Let the path consist of a single quantum channel
  (chain of states)
• Has quantum resistance R R0 1/G0 h/2q2
  12.9 k?.
• Then cE h/2 2.07 meV/THz (very low!)
• If path is at Tpath Troom 300 K, then cS
  0.08 k/THz.
• For N better efficiency than this, let the path
  consist of N parallel quantum channels. ? N
  lower resistance.
• What about systems where resistive models may not
  apply?
• E.g., superconductors, photonics, etc.
• A more general and rigorous (but perhaps loose)
  lower bound on the energy coefficient in all
  adiabatic quantum systems is given by the
  expression cE h2/4Egt?,
• where Eg energy gap between ground excited
  states,
• and t? time taken for a single orthogonalizing
  transition
• Ex. Let Eg 1 eV, t? 1 ps. Then cE 4.28
  µeV/THz.

35
Requirements for Energy-Recovering Clock/Power
Supplies

• All known reversible computing schemes require a
  periodic global signal that synchronizes and
  drives adiabatic transitions.
• For good system-level energy efficiency, this
  signal must oscillate resonantly and
  near-ballistically, with a high effective quality
  factor.
• Several factors make the design of a satisfactory
  resonator quite difficult
• Need to avoid uncompensated back-action of logic
  on resonator
• In some resonators, Q factor may scale
  unfavorably with size
• Effective quality factor problem
• Theres no reason to think that its impossible
  to do
• But it is definitely a nontrivial hurdle, that we
  need to face up to, pretty urgently
• If we want to make reversible computing practical
  in time to avoid an extended period of stagnation
  in computer performance growth.

36
The Back-Action Problem

• The ideal resonator signal is a pure periodic
  signal.
• A pretty general result from communications
  theory
• A resonators quality factor is inversely
  proportional to its signal bandwidth B.
• E.g., for an EM cavity w. resonant frequency ?0,
• the half-maximum BW is B ?? ?0/(2pQ) 1.
• Thus Q?8 ? B ? 0.
• There must be little or no information in the
  resonator signal!
• However, if the logic load being driven varies
  from on cycle to the next,
• whether due to data-dependent variations,
• or structural variations (different amounts of
  logic being driven per cycle)
• this will tend to produce impedance
  nonuniformities, which will lead to nonuniform
  reflections of the resonator signal
• and thereby introduce nonzero bandwidth into that
  signal.
• Even more generally, any departure of resonator
  energy away from its ideal desired trajectory
  represents a form of effective energy
  dissipation!
• we must control exactly where (into what states)
  all of the energy goes!
• the set of possible microstates of the system
  must not grow quickly

1 Schwartz, Principles of Electrodynamics,
Dover, 1972.
37
Unfavorable Scaling of Resonator Quality Factor
with Size?

• I dont yet have a perfectly clear and general
  understanding of this issue, but
• In a lot of oscillating systems Ive looked at,
  the resonant Q factor may tend to get worse (or
  at least, not very much better) as the resonator
  dimensions get smaller.
• E.g., in LC oscillators, inductor Q scales
  inversely to frequency
• EM emission is greater at high frequencies
• But, the tendency is for low f ? large coil
  sizes, not small!
• Anecdotal reports from people working in NEMS
  community
• It can be difficult to get high Q in nanoscale
  electromechanical resonators
• Perhaps due to present difficulty of precision
  engineering at nanoscale?
• Our own experience working with transmission-line
  resonators
• Example In a cubical EM cavity of length L,
• We have 2pQ L / 8d, where d skin depth. (1
  again)
• Skin depth d (2psk)-1/2, where s wall
  conductivity, k wave .
• So if L is fixed, high Q ? small d ? large k ?
  high f ? low Q in logic!

38
The Effective Quality Factor Problem

• Actual quality factor of resonator Q
  Eres/Edissr.
• Where Eres energy contained in resonator signal
• and Edissr energy dissipated in resonator per
  cycle.
• But the effective quality factor, for purposes of
  doing energy-efficient logic transitions is Qeff
  Edeliv/Edissr.
• Where Edeliv energy delivered to the logic per
  transition.
• Since 1/Qeff of the logic signal energy is
  dissipated per cycle.
• Thus, Qeff Q (Edeliv/Eres).
• That is, the effective Q is taken down by the
  fraction of resonator energy delivered to the
  logic per cycle.
• If a resonator needs to be large to attain high
  Q,
• it may also hold a large amount of energy Eres,
• and so it may not have a very high effective Q
  for driving the logic!

39
Trapezoidal Resonator Concept
(PATENT PENDING, UNIVERSITY OF FLORIDA)
Arm anchored to nodal points of fixed-fixed beam
flexures,located a little ways away, in both
directions (for symmetry)

z
y
Phase 180 electrode
Phase 0 electrode
Repeatinterdigitatedstructurearbitrarily
manytimes along y axis,all anchored to the
same flexure
x
C(?)
C(?)
0
360
0
360
?
?
40
Previous CMOS-MEMS Resonatorsin post-CMOS DRIE
process (in use at UF)
150 kHz
Resonators
41
PATENT PENDING, UNIVERSITY OF FLORIDA
Resonator Schematic
Actuator
Sensor
Sensor
Sensor
Sensor
Actuator
42
Post-TSMC35 AdiaMEMS Resonator
PATENT PENDING, UNIVERSITY OF FLORIDA
(Coventorware model)
Taped out April 04
Drivecomb
Sensecomb
Flexarm
43
Quasi-Trapezoidal MEMS Resonator 1st Fabbed
Prototype

• Post-etch process is still being fine-tuned.
• Parts are not yet ready for testing

Primaryflexure(fin)
Sensecomb
Drive comb
PATENT PENDING, UNIVERSITY OF FLORIDA
44
Conclusions

• Reversible computing will become necessary within
  our lifetimes,
• if we wish to continue progress in computing
  performance/power beyond the next 1-2 decades.
• Much progress in our understanding of RC has been
  made in the past three decades
• But much important work still remains to be done.
• I encourage my audience to join the community of
  researchers who are working to address the
  reversible computing challenge.