New Millennium EO1 Advanced Land Imager 23 January 1998

1
EO-1 WARP IT 8/20/98
NASA / Goddard Space Flight Center Swales
Aerospace Litton Amecom Daedalian
Systems Corporation
2
EO-1 WARP Memory Board 9/15/98
NASA / Goddard Space Flight Center Swales
Aerospace Litton Amecom Daedalian
Systems Corporation
3
EO-1 WARP RS-422 Input Board 5/4/98
Side A
Side B
NASA / Goddard Space Flight Center Swales
Aerospace Litton Amecom Daedalian
Systems Corporation
4
EO-1 Flight Data System Architecture
MIL-STD-1773
ALI MS/PAN
HSI VNIR SWIR
MIL-STD-1773
AC
CMD TLM point-to-point interfaces
RS-422 68 Mbps
RS-422 165 Mbps
RS-422 102 Mbps
RS-422 192 Mbps
4 Ch. RS-422 500 Mbps
MIL-STD-1773 (to/from ACDS)
WARP
ACDS
S-Band Data 2 Mbps
Reset (from ACDS)
X-Band Data 105 Mbps
S-Band RF
X-Band PAA
S-Band Uplink
S-Band Downlink
X-Band Downlink
5
EO-1 WARP Hardware Architecture
Power
Science Data Input
CMD/TLM Processing
Parallel RS-422 500 Mbps
S-Band Data 2 Mbps
1773 Bus RT 2
Modulated X-Band 105 Mbps
1773 Data Bus RT 1
28V Power
Reset
Downlink Output
Bulk Data Storage
WARP
X-Band I Q
Memory Board 24 Gbits
Memory Board 24 Gbits
FODB Input Board
Memory Interface Board
RF Exciter

Processor Board
LVPC
RSN
Data 250 Mbps
CMD/TLM
TLM
Data 1 Gbps
Data 1 Gbps
PWR
6
Hyperion Instrument to WARP Design Impact

• The Hyperion instrument channels will replace the
  ALI GIS channels.
• The RS-422 Input Card must accommodate the
  following interface differences
• Input Data Rates
• Clocking Scheme
• Frame Format
• Word Definition
• Bit Level Timing
• All design changes to the RS-422 board may be
  implemented inside a single FPGA.

7
12 1k x 36 FIFOs
54 HSC32s
EO-1 WARP RS-422 Input Card - Original Baseline
64
32
64310
32
Channel 1 Bits 310
Channel 1 Receivers
SWIR GIS
2
A14100 1
646332
9.6MHz
Channel 1 Bits 6332
9.6 MHz

• Header decode
• Input control
• Pixel packer
• Frame sync gen. and insertion

64310
32
64
32
Channel 2 Bits 310
Channel 2 Receivers
VNIR GIS
Notes - Only data flow lines are shown.
2
646332
4.8 MHz
Channel 2 Bits 6332
4.8 MHz
A14100 4
64
32
64310
32
Channel 3 Bits 310
Channel 3 Receivers
SWIR WIS
2

• Data block formatter
• FIFO control
• Block transmission to MIC
• MIC interface control
• Processor interface
• Circuit control state machine
• Status register bank
• Configuration register bank

A14100 2
646332
9.6 MHz
Channel 3 Bits 6332
To MIC
9.6 MHz

• Header decode
• Input control
• Pixel packer
• Frame sync gen. and insertion

64
64
64310
32
64
32
Channel 4 Bits 310
Channel 4 Receivers
VNIR WIS
2
646332
4.8 MHz
Channel 4 Bits 6332
4.8 MHz
64
32
64310
32
Channel 5 Bits 310
Channel 5 Receivers
MSPAN
2
A14100 3
646332
3.2 MHz
Channel 5 Bits 6332
3.2 MHz

• Header decode
• Input control
• Pixel packer
• Frame sync gen. and insertion

Receivers
64310
32
64
32
Data Processing/IO Control
Channel 6 Bits 310
Channel 6 Receivers
AC
Temporary Storage
2
646332
3.0 MHz
Channel 6 Bits 6332
3.0 MHz
8
12 1k x 36 FIFOs
54 HSC32s
64
32
64310
32
Channel 1 Bits 310
Channel 1 Receivers
EO-1 WARP RS-422 Input Card with Hyperion Addition
HSI SWIR
2
A14100 1
646332
8.2 MHz
Channel 1 Bits 6332
8.2 MHz

• Input control
• No header decode
• No pixel packing
• No FS insertion

64310
32
64
32
Channel 2 Bits 310
Channel 2 Receivers
HSI VNIR
Notes - Only data flow lines are shown.
2
646332
Channel 2 Bits 6332
5.0 MHz
5.0 MHz
A14100 4
64
32
64310
Channel 3 Bits 310
32
Channel 3 Receivers
NC
2
A14100 2
646332

• Data block formatter
• FIFO control
• Block transmission to MIC
• MIC interface control
• Processor interface
• Circuit control state machine
• Status register bank
• Configuration register bank

Channel 3 Bits 6332
9.6 MHz
To MIC
9.6 MHz

• Header decode
• Input control
• Pixel packer
• Frame sync gen. and insertion

64
64
64310
32
64
32
Channel 4 Bits 310
Channel 4 Receivers
NC
2
646332
Channel 4 Bits 6332
4.8 MHz
4.8 MHz
64
32
64310
Channel 5 Bits 310
32
Channel 5 Receivers
MSPAN
2
A14100 3
646332
3.2 MHz
Channel 5 Bits 6332
3.2 MHz

• Header decode
• Input control
• Pixel packer
• Frame sync gen. and insertion

Receivers
64310
32
64
32
Channel 6 Bits 310
Data Processing/IO Control
Channel 6 Receivers
AC
Temporary Storage
2
646332
Channel 6 Bits 6332
Hyperion Interface Changes
3.0 MHz
3.0 MHz
9
WARP Hyperion Enhancement Plan

• Complete the new Hyperion RS-422 Data Interface
  FPGA
• At a convenient breaking point, install the FPGA
  in the existing RS-422 Input Board
• Perform RS-422 Input Board Bench-Testing (verify
  hyperspectral channels)
• RS-422 Input Board Built-In-Test Mode
• WARP Science Data Simulator GSE Test Mode
• TRW Hyperion Data Interface Simulator?
• Perform Box-Level End-To-End Verification (verify
  hyperspectral channels)
• Proceed with WARP IT