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20071009 HW

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... circuit architecture (by drawing), Verilog code, test bench, simulation waveform ... C program that can generate the Verilog file of the adder/subtractor circuits ... – PowerPoint PPT presentation

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Title: 20071009 HW


1
2007/10/09 HW
  • (10) Please complete the hardware of 4-bit full
    adder and subtractor, respectively.
  • (20) Please combine these two hardware into one
    and to form the 4-bit adder/subtractor by setting
    the value of cin, if cin0 then perform addition,
    else perform subtraction.
  • (20) Please add OVERFLOW detection circuit to
    indicate the result is overflow, except some
    inputs that wont cause overflow, your test data
    must contain the following inputs that will cause
    overflow
  • a0001, b0111, cin0
  • a1001, b1010, cin0
  • a1001, b0111, cin1
  • a0111, b1001, cin1

2
2007/10/09 HW (contd)
  • (20) Use your designed 4-bit adder/subtractor
    with overflow detection to design an 8-bit
    adder/subtrcotr with overflow detection, your
    report must contain your circuit architecture (by
    drawing), Verilog code, test bench, simulation
    waveform and your descriptions about simulation.
  • (30) Write a C program that can generate the
    Verilog file of the adder/subtractor circuits
    automatically once the user inputs the bit-width
    of the adder. For example, if user inputs n8,
    your program can generate the contents (including
    the Verilog file and the corresponding test bench
    for the circuits) for the adder/subtractor
    circuits. You must upload your C file to the ftp
    site by naming the filename as your student
    number, too. (If your program can generate Ripple
    Carry Adder/subtractor 1-bit module by another,
    you will get 10, if your program can generate
    adder/subtractor 4-bit module by 4-bit module
    consectively, your will get 30!)
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