Design using HDLs

1
Design using HDLs

• VHDL vs. Verilog
• Similarities Differences

2
Background

• VHDL development sponsored by the US-DoD and the
  IEEE in mid 80s
• VHDL became IEEE standard 1076 in 1987
• VHDL versions VHDL-87, VHDL-93, VHDL-2001

• Verilog was launched by Gateway in 1983 which was
  bought by Cadence in 1989
• Cadence opened Verilog to the public domain in
  1990
• Verilog became IEEE Standard 1364 in 1995
• Verilog versions Verilog 1995, Verilog 2001

• Both VHDL and Verilog are Industry Standards
• Both can be used to implement algorithms for
  specification simulation or synthesis purposes
• Both can be used for structural or behavioral
  design modeling

3
Common Characteristics

• Look similar to conventional programming
  languages
• However, they have a significant difference with
  regards to programming languages they are
  inherently Parallel
• Allow different levels of abstraction
• Behavioral
• Result ab c mod i
• Structural

4
Design ShellsVHDL - Verilog

• ENTITY mux IS
• PORT (
• a IN BIT
• b IN BIT
• c IN BIT
• d IN BIT
• s0 IN BIT
• s1 IN BIT
• x OUT BIT)
• END mux
• ARCHITECTURE dataflow OF mux IS
• . . .
• END dataflow

• module mux (
• a,
• b,
• c,
• d,
• s0,
• s1,
• x )
• input a, b, c, d, s0, s1
• output x
• . . .
• endmodule

5
Parameterized Design ShellsVHDL - Verilog
ENTITY mux IS GENERIC ( W POSITIVE 3) PORT
( a, b, c, d IN BIT_VECTOR (W downto 0) s0
IN BIT s1 IN BIT x OUT BIT_VECTOR (W
downto 0) ) END mux ARCHITECTURE dataflow OF mux
IS . . . END dataflow -- Parameterized
Instantiations U1 mux GENERIC MAP (8) PORT MAP
(d1,d2,d3,d4,s0,s1,out)
module mux ( a, b, c, d, s0, s1, x )
parameter W 3 input W0 a, b, c, d
input s0, s1 output W0 x . . .
endmodule // Parameterized instantiations mux
(7) mx1(d1,d2,d3,d4,s0,s1,out) mux (1)
mx2(f1,f2,f3,f4,s0,s1,out)
6
Design InstantiationVHDL - Verilog
Using Positional Association ARCHITECTURE struct
OF logic IS COMPONENT and2 PORT (a, b IN
BIT c OUT BIT) END
COMPONENT SIGNAL a1, a2, b1, b2, c1
BIT BEGIN U1 and2 PORT MAP (a1, a2,
b1) U2 and2 PORT MAP (b1, b2, c1) . . .
Using Positional Association module logic ( . .
. ) input . . . wire a1, a2, b1, b2,
c1 and2 u1 (a1, a2, b1) and2 u2 (b1, b2,
c1) . . . endmodule
7
Design InstantiationVHDL - Verilog
Using Explicit Association ARCHITECTURE struct
OF logic IS COMPONENT and2 PORT (a, b IN
BIT c OUT BIT) END
COMPONENT SIGNAL a1, a2, b1, b2, c1
BIT BEGIN U1 and2 PORT MAP (agta1, bgt
a2, cgt b1) U2 and2 PORT MAP (cgt c1, agt
b1, bgt b2) . . .
Using Explicit Association module logic ( . .
. ) input . . . . . . wire a1, a2, b1,
b2, c1 and2 u1 (.a(a1), .b(a2), .c(b1)
) and2 u2 (.c(c1), .a(b1), .b(b2) ) . .
. endmodule
Sequence of instantiation does not matter!
8
Data TypesVHDL - Verilog

• bit 1
• bit_vector 1001
• boolean true
• character a
• integer 139
• natural 0
• positive 1
• real -2.3
• time 5 ns

• bit 0,1,x,z
• integer 10
• real 4.3

All the above data types are included in the
standard library library std use
std.standard.all
Not supported by Synthesis tools
9
More TypesVHDL

• type STD_ULOGIC is (
• U, -- uninitialized
• X, -- forcing unknown
• 0, -- forcing 0
• 1, -- forcing 1
• Z, -- high impedance
• W, -- weak unknown
• L, -- weak 0
• H. -- weak 1
• -) -- dont care
• STD_LOGIC
• STD_ULOGIC_VECTOR
• STD_LOGIC_VECTOR
• library ieee use ieee.std_logic_1164.all

• User can define similarly custom data types
• TYPE small_int IS range 0 to 1024
• TYPE word_len IS 31 downto 0
• TYPE opcod IS (load,store,add,sub)
• or subtypes
• SUBTYPE scale IS integer RANGE -1024 TO
  1024
• VHDL is strongly-typed, and thus assignments can
  occur only between signals of the same type.
  However, assignment between a type and its
  subtypes is allowed

10
ArraysVHDL - Verilog

• Declaration
• TYPE word IS ARRAY (15 downto 0) of std_logic
• TYPE vector IS ARRAY (natural range ltgt) of
  integer
• TYPE matrix3x2 IS ARRAY (1 to 3, 1 to 2) of
  natural
• Instantiation
• VARIABLE data_arr matrix3x2
  ((0,2),(1,3),(4,6))
• Array access
• data_arr(3,1)

• Declaration
• wire 150 word
• wire 13 matrix3x2 12
• Array access
• word1
• matrix3x223

11
Data ObjectsVHDL - Verilog

• constant (declared at the start of an
  architecture)
• signal (gets updated a delta delay after its
  assignment statement is executed)
• variable (only exist and are used in procedural
  blocks)

• parameter (used as a constant)
• wire (used in concurrent assignments)
• wand (wired-AND)
• Wor (wired_OR)
• tri (tri-state)
• supply0
• supply1
• reg (used in procedural assignments, data is
  stored in unsigned format for multi-bits)
• input, output, inout (By default are of type
  wire, but can be configured as any of the above
  types, with the exception of parameter)

12
OperatorsVHDL - Verilog
Relational Equality / Inequality !
lt Less Than lt lt Less Than or
Equal lt gt Greater Than gt gt Greater Than
or Equal gt Logical/Bitwise AND and /
OR or / NOT not ! /
XOR xor N.A / NAND nand N.A. NOR nor
N.A. XNOR xnor N.A /
13
Operators (2)VHDL - Verilog
Arithmetic addition - subtraction -
multiplication / division / MOD modu
lus REM Remainder N.A. Shift SLL shift
left logical ltlt SRL shift right
logical gtgt SLA shift left arithmetic N.A. SR
A shift right arithmetic N.A ROL rotate
left N.A. ROR rotate right N.A.
14
Operators (3)VHDL - Verilog
Arithmetic exponentiation ABS absolute
value Concatenation
Reduction reduction and reduction
or reduction nand reduction
or reduction xor reduction xnor
Concatenation n n-Replication ?
Conditional
15
Concurrent StatementsVHDL - Verilog
Simple Signal Assignment sum lt (a XOR b) XOR
cin carry lt a AND b Conditional
Signal Assignment z lt a WHEN s10 AND s00
ELSE b WHEN s10 AND s01 ELSE c WHEN s11
AND s00 ELSE d Selected Signal
Assignment WITH sel SELECT z lt a WHEN
00, b WHEN 01, c WHEN 10, d WHEN 11
Simple Signal Assignment assign sum (a b)
cin assign carry a b Conditional
Signal Assignment assign z lt s1? (s0 ? d c)
(s0 ? b a)

• Priority is inferred based on the order of
  selection values

• No two choices can overlap
• All ppossible cases must be covered if when
  others is not present
• All options have equal priority

16
Combinational Procedures asConcurrent
StatementsVHDL - Verilog

• Combinational process
• PROCESS (a, b, c)
• BEGIN
• IF (c 1) THEN
• out lt a
• ELSE
• out lt b
• END IF
• END PROCESS
• Sensitivity list is usually ignored during
  synthesis (it must contain all read signals)
• Sensitivity list can be replaced by WAIT ON
  a,b,c at the end of process
• Use either WAIT ON or Sens. List, NOT both

• Combinational procedure
• always_at_(a or b or c)
• begin
• if ( c )
• out lt a
• else
• out lt b
• end
• Make sure there are no missing clauses (otherwise
  a latch may be inferred)
• Latches should be avoided in synchronous designs
• In Verilog 2001, sensitivity list can be replaced
  by star () which substitutes all the read signals

17
Clocked Procedures as Concurrent
StatementsVHDL - Verilog

• Sequential process
• PROCESS (clk)
• BEGIN
• IF (clkEVENT AND clk 1) THEN
• IF (c 1) THEN
• out lt a
• END IF
• END IF
• END PROCESS
• Sensitivity list must only contain clock signal

• Sequential procedure
• always_at_(posedge clk)
• begin
• if ( c )
• out lt a
• end
• Missing clauses do not infer any latches in this
  case
• Two types of assignment
• non-blocking ( lt )
• blocking ( )
• Use non-blocking for sequential procedures

18
Synchronous / Asynchronous Reset in Clocked
ProceduresVHDL - Verilog

• Synchronous Reset
• PROCESS (clk)
• BEGIN
• IF (clkEVENT AND clk 1) THEN
• IF (rst 1) THEN
• out lt 0
• ELSE
• out lt a
• END IF
• END IF
• END PROCESS
• Asynchronous Reset
• PROCESS (clk, rst)
• BEGIN
• IF (rst 1) THEN
• out lt 0
• ELSIF (clkEVENT AND clk 1) THEN
• out lt a
• END IF

• Synchronous Reset
• always_at_(posedge clk)
• begin
• if ( rst )
• out lt 0
• else
• out lt a
• end
• Asynchronous Reset
• always_at_(posedge clk, posedge rst)
• begin
• if ( rst )
• out lt 0
• else
• out lt a
• end

19
Types of Procedural Assignments VHDL - Verilog

• Both Variables and Signals can be assigned within
  procedures
• lt signal assignments
• Evaluated in parallel regardless their order
• Should be preferred in sequential procedures to
  implement flip-flops
• variable assignments
• Evaluated in the order statements are written
• Good for algorithm implementation with
  combinational logic
• Variables only accessible within procedure
• registers are generated for variables that might
  be read before being updated!

• Only reg objects can be assigned within
  procedures
• lt non-blocking assignments
• Evaluated in parallel regardless their order
• Should be used in sequential procedures to
  implement flip-flops
• Good to use when same variable appears in both
  sides of lt
• blocking assignment
• evaluated in the order statements are written
• Should be used for combinational logic
• For synthesis should not mix different types of
  assignments in the same procedure

20
if statements VHDL - Verilog
z lt a IF (x 1111) THEN Z lt B ELSIF (x gt
1000) THEN z lt c END IF
IF (x 1111) THEN z lt b ELSIF (x gt 1000)
THEN z lt c ELSE z lt a END IF
z a if (x 4b1111) begin z lt b end else
if (x gt 4b1000) begin z c end
if (x 4b1111) begin z lt b end else if (x
gt 4b1000) begin z c end else begin z
a end

• Used only within procedures
• Conditions might overlap
• Processed sequentially and thus implies priority
  (statements within first true condition will be
  executed)
• Instead of an else clause a default statement
  may be used before if elsif statement (as
  shown in above example)
• All cases should be covered in order to avoid
  latch inference

21
case statements VHDL - Verilog
CASE x IS WHEN 0000 gt z lta WHEN 0111
1001 gt z lt b WHEN OTHERS gt z lt
0 END CASE
case (x) 4b0000 z a 4b0111, 4b1001
z b default z 0 endcase

• Used only within procedures
• case options must not overlap
• All choice options have to be covered
• All branches equal in priority
• when others covers all remaining choice options

• Used only within procedures
• case options can overlap
• All choice options should be covered to avoid
  latch inference
• Higher branches have bigger priority
• Special directives are supported by CAD vendors
  to infer equal priority muxs
• default covers all remaining choice options

22
Misc. syntax differencesVHDL - Verilog

• Case Insensitive
• Identifiers and keywords are case insensitive,
  e.g. sum and SUM refer to the same data object
• -- This is a Comment
• Bit Strings
• B1100_1001 -- Binary representation
• XC9 -- Hex representation

• Case sensitive
• Identifiers and keywords are case sensitive, e.g.
  sun and SUM refer to different data objects. Mind
  this when working on mixed HDL designs
• // This is a Comment
• / This is also
• a comment /
• Bit Strings
• 8b1100_1001
• 8hc9

23
Epilogue

• Both Languages are well equipped for modeling
  digital synchronous circuits
• Both are well supported by Simulation and
  Synthesis CAD tools
• VHDL is more strongly typed than Verilog and thus
  places extra restrictions on the modeling of
  integrated circuits (many data types, required
  conversions between types, etc.)
• Verilog easier to learn for the 1st time user,
  but more prone to mistakes due to careless
  modelling (VHDL more robust in this sense)
• Verilog more C like. VHDL heavily based on Ada
• VHDL offers bigger variety of concurrent
  constructs, as well as high level modeling
  constructs (e.g. packages, configurations)
• Good to know both of them, as mixed HDL designs
  are frequently used