Lab4 Tutorial using HDL Based Design

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Lab4Tutorial using HDL Based Design

• Verilog Language

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Objective

• This tutorial will give you exposure to using HDL
  based design
• Using Verilog and Modelsim for simulating the
  functional design
• This tutorial shows you how to create, using
  Verilog, a simple combinational logic circuit
  design

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Logic Function
F(xy)(yz)
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Logic Circuit
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Implementation Methods

• Method 1 Using the automatic module generator
• Method 2 Using the user free input

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Method 1

• Using the automatic module generator

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Create a New Project
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Enter a Name and Location for the Project
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1
3
4
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Select the Device and Design Flow for the Project
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2
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Create a New Source
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Select Verilog Module and Enter File Name
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1
3
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Define Verilog Source
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New Source Information
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Next Step
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Next Step
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Finish
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Input Logic Function
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Add Test Bench Source
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Add Test Bench Waveform
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1
3
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Select Source File
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2
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New Source Information
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Initialize Timing
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Waveform Created by HDL Bencher
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Save the Waveform
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View Behavioral Text Fixture
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Simulate Behavioral Model
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ModelSim Windows
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Wave Window
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Verifying the Logic Function F(x y)(yz)
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Question and Answer
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Method 2

• Using the user free input

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Design a Logic Circuit
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Create a New Project
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Enter a Name and Location for the Project
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1
3
4
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Select the Device and Design Flow for the Project
1
2
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Create a New Source
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Next Step
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Finish
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Create a New File
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Free Input Verilog Language in the New File
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Design Using RTL Level
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Design Using Gate Level
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Save the Design
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File Name logic.v

• Module name and File name must the same.

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Add Source into the Project
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Select logic.v
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Choose Source Type
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Add New Source for Test Bench Waveform
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Select Test Bench Waveform
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1
3
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Initialize Timing
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Waveform Created by HDL Bencher
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Giving Input Values
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Save the Waveform
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Select View Behavioral.. and Run
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See a HDL Test bench
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Select Generate Expected.. and Run
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Verifying the Function of F(x y)(yz)
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Question Answer