Title: Chap' 3 Basic Concepts
1Chap. 3 Basic Concepts
2Basic Concepts
- Lexical Conventions
- Data Types
- System Tasks and Compiler Directives
- Summary
3Lexical Conventions - I
- Whitespace
- Blank space (\b)
- Tabs (\t)
- Newlines (\n)
- Comments
- // single line
- / / multiple line
- Operators
- Unary ?!
- Binary ?-?
- Ternary a b ? c d
4Lexical Conventions - II
- Number Specification
- Sized numbers ltsizegtltbase formatgtltnumbergt
- 4b1111
- 12habc
- 16d255
- Unsized numbers
- 23456
- hc3
- o21
- X (unknown) and Z (high impedance)
- 12h13x
- 6hx
- 32bz
- Negative numbers
- -8d3
- Underscore characters and Question marks
- 12b1111_0000_1010 equals to 12b111100001010
- 4b10?? equals to 4b10zz
5Lexical Conventions - III
- String
- Hello Verilog World
- a/b
- Identifiers and Keywords
- reg value
- input clk
6Basic Concepts
- Lexical Conventions
- Data Types
- System Tasks and Compiler Directives
- Summary
7Data Types
- Value set and strength
- Nets
- Registers
- Vectors
- Integer?Real and Time Register Data Types
- Arrays
- Memories
- Parameters
- Strings
8Value Set and Strength
9Nets
- Declare a physical wire
- Keyword wire?wand?wor?tri?trior?trireg
- wire a
- wire b, c
- wire d 1b0
a, b, c are wires (nets).
10Registers
- Storage element for data
- Do not equal to hardware register
- Similar to variables in C
reg reset initial begin reset 1b1
100 reset 1b0 end
11Vectors - I
- wire and register can be defined as vector form
- format
- highlow or lowhigh
wre a wire 70 bus wire 310 busA, busB,
busC reg clock reg 040 virtual_addr
12Vectors - II
- Subset of vector
- Partial bits of vector
busA7 Bus20 Virtual_addr01
13Vectors - III
- Fixed width subset
- ltstarting_bitgtwidth or ltstarting_bitgt-width
reg 2550 data1 reg 0255 data2 reg 70
byte byte data131-8 // data13124 byte
data1248 // data13124 byte
data231-8 // data22431 byte
data2248 // data22431 for (j0 jlt31
jj1) // 70, 158255248 byte
data(j8)8 data1(byteNum8)8 8b0
14Integer, Real, and Time Register Data Types I
- Integer can represent signed number
- Real
integer counter initial counter -1
real dalta initial begin delta 4e10
delta 2.13 end integer i initial i
delta // rounded value of 2.13
15Integer, Real, and Time Register Data Types II
- Time
- Storing simulation time
time save_sim_time initial save_sim_time
time
16Arrays - I
- Type integer, register, time, real, or vector.
- Dimension no limit, but dimension must be
constant - Format
- ltarray_namegtltsubscriptgt
integer count07 reg bool310 time
chk_point1100 reg 40 port_id07 integer
matrix400255 reg 630 array_4d
15070702550 wire 70 w_array2
50 wire w_array17050
17Array - II
count5 0 chk_point100 0 port_id3
0 matrix10 33559 araay_4d0000150
0fff port_id 0 // error usage matrix1
0 // error usage
18Memories
reg mem1bit 01023 reg 70 membyte
01023 membyte511
19Parameters
- Define a constant
- Can be re-defined at topper level using
defparam - localparam (Verilog 2001 new feature)
- Can not be re-defined by defparam
parameter port_id 5 parameter cache_line_width
256 parameter signed 150 WIDTH
20Strings
- Can be assigned to register
reg 8181 string_value initial
string_value Hello Verilog World
21?3-3 ????
22Basic Concepts
- Lexical Conventions
- Data Types
- System Tasks and Compiler Directives
- Summary
23System Tasks
- Displaying information
- Monitoring information
- Stopping and finishing
24Displaying information - I
- display (p1, p2, p3,, pn)
- Like printf in C
- Format specification list
25Displaying information - II
26Displaying information - III
27Displaying information - IV
28Monitoring Information
- monitor(p1,p2,, pn)
- Monitor signal change and output the change
29Stopping and finishing
- stop stop simulation and enter interactive mode
to debug - finish end of simulation
30Compiler Directives
- define
- Define text macro, like define in C
- include
- Include the context of another file, like
include in C
31Usage of define
32Usage of include
33Basic Concepts
- Lexical Conventions
- Data Types
- System Tasks and Compiler Directives
- Summary
34Summary
- Verilog is similar to C
- Lexical conventions
- Data Types
- Value set, wire, register, vector, integer, real,
time, array, memory, parameter, string - System Tasks
- display, monitor, stop, finish
- Compiler Directives
- define and include