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Synopsys overview

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Verilog-A(MS) Virtual Test Bed. fREEDA. 9. Paragon Architecture. Editors. State Machine ... Code generation support for Verilog-A(MS) Digital modeling ... – PowerPoint PPT presentation

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Title: Synopsys overview


1
ParagonDefining New VTB Models
H. Alan Mantooth September 18, 2003 Department of
Electrical Engineering University of
Arkansas Fayetteville, AR 72701 mantooth_at_engr.uark
.edu
2
Outline
  • Introduction
  • Modeling Approaches Strategy
  • Paragon Architecture
  • Paragon Illustrations
  • Progress Update
  • Scope and Conclusions

3
Introduction
  • Complex systems require mixed-level modeling and
    simulation for effective verification and design
    exploration
  • Successive design exploration
  • traditional system partitioning/decomposition
  • automated approaches involving synthesis
  • Design analysis and performance verification will
    demand bottom-up approaches to behavioral model
    creation
  • Circuit designers dont have a propensity to
    write programs, but they will use analysis tools

4
Paragon
  • Why are such tools needed?
  • Simulator vendors dont have all the models
  • HDLs are used to describe the behavior of models

  • Should a modeler know all HDLs?
  • Simulation takes a long time
  • Modeling takes even longer time
  • Paragon - Mixed Signal Language Independent
    Behavioral Modeling environment

5
Modeling Approaches
6
Paragon Products
7
Modeling Strategy Outside-in
Enter Public Interface
8
Modeling Strategy (contd)
Analyze model robustness
  • Mast
  • VHDL-AMS
  • Verilog-A(MS)
  • Virtual Test Bed
  • fREEDA

9
Paragon Architecture
10
Achieving Language Independence
  • Generation of Multiple HDLs using a neutral
    intermediate representation
  • Internal Format - XML(Extensible Markup Language)
    and MathML
  • MathML - XML application for describing
    mathematical applications
  • Why XML?
  • Simple and flexible structured format
  • Standardization and Open sourcing
  • Enables sharing models independent of any HDL
  • Powerful and efficient way of expressing and
    manipulating data
  • Easier to work with data from database
  •  

11
Example
  • Example of a Resistor model in XML database
  • ltbranch from"elec1" nameresistor" to"elec2"gt
  • ltquantity name"i" nature"through"
    type"current" unit"ampere" /gt
  • ltquantity name"v" nature"across" type"voltage"
    unit"volt" /gt
  • ltequation gt
  • ltmrowgt
  • ltmigtvlt/migt
  • ltmogtlt/mogt
  • ltmigtilt/migt
  • ltmogtlt/mogt
  • ltmigtresistancelt/migt
  • lt/mrowgt
  • lt/equationgt
  • lt/branchgt

12
Analysis Methods
  • Features of Abstract Syntax Tree (AST)
  • Represent internal relationships for variables
    of a model
  • Determines the functional and time dependencies
  • Checks for discontinuities in the model

If Vgs lt Vt Ids 0 Elseif Vgs Vt lt
Vds Ids ß ( (Vgs Vt))/2) Else
Ids ß((Vgs Vt) Vds ((Vds 2)/2)) Endif
13
Paragon VTB Design Flow
Paragon
VTB
User Input
C Files
Interface
XML-Database
UDD tool
Vtm File
Analysis
Model Database
Internal Form
14
Paragon Illustrations
  • EKV 2.6 MOSFET Model (Analog)
  • Solenoid (Multi Domain)
  • Three Phase Source (VTB/Paragon)

15
EKV 2.6 MOSFET
16
EKV 2.6 MOSFET Topology
17
EKV 2.6 MOSFET Curves
  • Simulated in Freeda (Hand Written (7 weeks) Vs
    Paragon Generated Code (1 week) )

18
Solenoid Model (VHDL-AMS)
  • Simulated in System Vision (Mentor Graphics)

19
VHDL-AMS code(Solenoid)
library IEEE library IEEE_proposed use
IEEE.math_real.all use IEEE_proposed.electrical_s
ystems.all entity solenoid is generic
(F_maxreal2.0 F1real1.0
damp_stopreal30.0 dreal0.1 i0real2.0
kreal50.0 mreal0.02k_stopreal1.
0e6 gap1real0.004 pos_minreal0.0
r_windreal1.0 pos_maxreal0.004
length_f0real0.01) port (terminal EM
translational terminal EC1 electrical terminal
EC2 electrical) end entity solenoid architectur
e Arch1 of solenoid is constant k_1 real
((sqrt(F_max/F1)-1.0)/gap1) constant L_max real
((2.0F_max)/((i02.0)k_1)) quantity tforce
through EM to translational_ref quantity gap
across EM to translational_ref quantity tforce1
through EM to translational_ref quantity force2
through EM to translational_ref quantity force3
through EM to translational_ref quantity force4
through EM to translational_ref
20
VHDL-AMS code(Solenoid)
  • quantity i through EC1 to EC2
  • quantity v across EC1 to EC2
  • quantity velreal1.0
  • quantity accelreal1.0
  • quantity velocity_damperreal1.0
  • quantity velocityreal1.0
  • quantity lreal1.0
  • quantity mfluxreal1.0
  • quantity tforce_tempreal1.0
  • quantity force4_tempreal1.0
  • begin
  • velgap'dot
  • accelvel'dot
  • velocity_dampergap'dot
  • velocitygap'dot
  • tforce1(m accel)
  • force2(k(gap-length_f0))
  • force3(d velocity_damper)
  • force4force4_temp

21
VHDL-AMS code(Solenoid)
  • v((i r_wind)mflux'dot)
  • tforce tforce_ temp
  • if (gap'above (pos_max)) use
  • force4_temp((k_stop(gap-pos_max))(damp_stopve
    locity))
  • elsif (gap'above (pos_min)) use
  • force4_temp0.0
  • else
  • force4_temp((k_stop(gap-pos_min))(damp_stopve
    locity))
  • end use
  • break on gap'above (pos_min),gap'above (pos_max)
  • mflux li
  • if not (gap'above (0.0)) use
  • lL_max
  • tforce_tempF_max(i2.0)/(i02.0)
  • else
  • l(L_max/(1.0(k_1gap)))
  • tforce_temp0.5k_1L_max(i2.0)/((1.0k_1gap)
    2.0)
  • end use
  • break on gap'above (0.0)

22
Three Phase Source (VTB)
Layers 3 Nodes 4, Terminals 4 Parameters
R, Vm Identifiers g, f
23
Three Phase Source in Paragon
24
Three Phase Source in Paragon
25
Future of Paragon-VTB environment
Paragon
VTB
User Input
VHDL-AMS
C Files
XML-Database
Reader
Vtm File
Analysis
Model Database
Internal Form
26
Future Paragon Enhancements
  • Silicon Carbide Device Modeling into VTB through
    Paragon
  • SRC/Darpa project to open source XML database
  • Model reading technology
  • Further support for Mast
  • Code generation support for Verilog-A(MS)
  • Digital modeling
  • Integration of Spice C code generator

27
Conclusions
  • The models can be generated in a number of
    hardware description language formats including
    native VTB
  • Paragon is an extensible environment that will
    accommodate bottom-up methods as well
  • Model testing and validation are integral to the
    process
  • Further extensions in mixed-signal
  • Paragon allows designers to create behavioral
    models in a top-down, language-independent fashion
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