CS 140L Lecture 6

1
CS 140L Lecture 6

• Professor CK Cheng
• 11/05/02

2
Lab 3 Finite State Machine

1. Design Flow
2. Xilinx Process
3. Transformation from Mealy to Moore machine
4. State Assignment

Design Process
State Diagram Logic Synthesis Placement
Routing FPGA
(Graphic I/O)
Mealy Moore
Verilog, VHDL, ABEL
3
Xilinx Process

1. Project Manager.
2. New project Family Spartan, Device S05PC84,
   Speed 4.
3. State Diagram (ABEL).
4. Create Macro Component ? State Diagram
5. Schematic Diagram Call the component (Either on
   top or bottom of list).
6. Synthesis.

CLK
rst
Z
x
CLB
7. Timing Diagram. 8. Check Layout CLBs
(blocks)
4
3. Transformation from Mealy to Moore Machine
Moore Machine y(t) f(x(t), s(t)) Mealy
Machine y(t) f(s(t)) s(t1) g(x(t), s(t))
x(t)
x(t)
C1
C2
y(t)
C1
C2
y(t)
CLK
CLK
s(t)
s(t)
Moore Machine
Mealy Machine