Joe Jones

1
Group IV

• Joe Jones
• J. D. Pineda
• John Carroll
• Jesus Velasquez
• Advisor Dr. Saed

2
Presentation Outline
1. Project Assignment
2. Transmitter
3. Tuning Amp Layout Rec./Tran.
4.Software
5. Demodulation
6. Gantt Chart and Budget
3
Transmitter Block Diagram
Pineda
4
Controller
Pineda
5
RF Amplifier

• Mini-Circuits
• DC-1.5 GHz
• 60mA 4.5V
• ERA-50SM
• 2.95

Pineda
6
Transmitter Layout
Pineda
7
Transmitter Board
Pineda
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Measurements Filter Amp.
Pineda
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From DDS
Pineda
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Output Filter Amp
Pineda
11
MAX436 Tuned Amplifier

• A 4Mhz crystal was used for the resonance
  frequency.

Joe
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MAX436 results

• The top graph is the result with the input
  frequency set at 4Mhz.
• The bottom graph has a deviation of 400Hz on the
  input.

Joe
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MAX436 Amplifier
Joe
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P-spice results
Joe
15
Layout through completed board
Joe
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Amplifier Results

• The amplifier seems to be tuning but the gain is
  low.
• At the 75.5Mhz the gain is 4.18dBm.
• The input is set at 0dBm.

Joe
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Receiver layout
Joe
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Etched Receiver Board
Joe
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Etched Transmitter Board
Joe
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Filter Schematic
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Filter Simulation
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Output of DDS
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Output of Filter
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Output after Amplification
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Tuning Word Output
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Clock Output
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Bit Time
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Re-synchronization
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Demodulation Using PLL
Phase Lock Loop Basic Operation

• Generally the circuit accepts input at some
  frequency and providing an output at the same
  frequency that is not identical.
• The output of the VCO is compared to the input,
  and if the frequencies differ, oscillator is
  altered to reduce difference
• The phase comparator compares the phases of its
  two input waves and provides an output V1
  proportional to the phase difference

Jesus Velasquez
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PLL Testing
Fmark
Fspace
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Fairchild 74VHC4046

• R1 and C1 determine VCO frequency range
• R2 Enables the VCO have a frequency offset
• Rs Resistor for demodulator output
• 3 Types of comparators to choose from
• C1 is 2200pf and R2 used 5k potentiometer to
  fine tune offset frequency
• R1 after testing is 10k
• Low pass filter R3 is 5k and C2 is 0.012 uf

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Test Results for PLL
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Demodulation Results
Output from the PLL demodulation pin
Output from the Voltage comparator pin
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Final Circuit (PSpice)
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Final Circuit (Breadboard)
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Final Circuit
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(No Transcript)
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References

• Jack Smith, Modern Communication Circuits,
  Pg188-Pg198 (AGC)
• Dr. Saed
• MSP430 F149 Data Sheet
• MSP430X1XX Users Guide
• MSP430 Code examples
• Dr. Nutter
• Dr. Dickens
• www.ti.com
• Roland E. Best, Phase-Locked Loops, Pg 96-100
  (PC)
• Ryan Casey

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Gantt Chart