365 Computer Architecture

1
365 Computer Architecture

• Week 2 Lecture 4
• Soundararajan Ezekiel
• Department of Computer Science
• Ohio Northern University

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Chapter 1, 2 Overview

• Performance metrics
• Know how to compare 2 machines machine A is XXX
  times faster than machine B
• Need to know exactly what we are measuring
  time, rate, throughput, CPI, cycles, etc
• Need to know how combining these to give
  aggregate numbers does different kinds of
  distortions to the individual numbers
• No metric is perfect, so lots of emphasis on
  std. benchmarks today

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Fair comparison

• Comparing 2 machines running the same benchmark
  always use the execution time for comparison
• Comparing 2 machines running a set of
  benchmarks use weighted execution time
  (arithmetic mean)
• Comparing 2 or more machines, normalize perf.
  w.r.t. a reference machine use geometric mean
• Amdahls Law
• Speedup is limited by the fraction which is not
  optimized

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Plan for today

• ISA (Instruction Set Architecture) and Assembly
  Language
• Instruction Set Definition (MIPS)
• Registers and Memory
• Arithmetic Instructions
• Load/store Instructions
• Instruction Formats
• Summary

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Instruction Set Architecture ISA

• Interface between Hardware and Software

Assembly Language
Application Software
OS
compiler
Instruction set Architecture ISA
Instruction set processor
I/O System
Machine Language
Digital design
Circuit design
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Classify ISA

• Internal storage in the CPU is the most basic
  differentiation
• Alternative for this portions of the
  architecture
• Stack, Accumulator or set of registers
• Stack Architecture are implicitly on top of stack
• accumulator architecture one operands is
  implicitly the accumulator
• general purpose register architecture either
  register or memory

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Continue
Stack Accumulator
Register
Register (register-memory)
(load-store)

• CAB
• register-memory architecture memory as a part
• load-store or register-register architecture
• memory-memory architecture is not found in modern
  computers(keeps all operands in memory)

Push A Load A
Load R1, A
Load R1, A
Push B Add B
Add R1, B
Load R2, B
Add Store C
Store C, R1
Add R3,R1,R2
Pop C

Store C,R3
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continue

• early machines used stack or accumulator-style
  architecture
• Machine design after 1980 uses load-store
  register architecture
• Reason(General Purpose Registers GPR)
• Registers like other form of storage-- faster
  than memory
• registers are easier for a compiler to use
• Example (AB)-(CD)-(EF)---- multiply any order
  --- BUT stack machines evaluated left to right

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continue

• important registers can be used to hold
  variables--when variables are allocated to
  registers, the memory traffic reduces, program
  speeds up (registers are faster than memory) code
  density improves( register can be named with
  fewer bits than memory)
• compiler writers would prefer all registers be
  equivalent and unreserved
• older machines compromise this desire by
  dedicating registers to special uses, decrease GPR

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Continue

• How many registers are sufficient?
• Depend on how they are used by compilers
• some compilers reserve some registers for
  expression evaluation, use some for parameter
  passing, and allow the remainder to be allocated
  to hold variables
• With the class of Architecture covered , the next
  topic is addressing operands

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Memory

• Independent of register-register architecture or
  allows any memory reference
• How memory address are interpreted?
• How they are specified?
• We will deal with these two topics

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Interpreting Memory Addresses

• How is a memory address interpreted?
• That is, what object is accessed as a function of
  the address and the length?

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Memory organization

• Viewed as a large, single-dimension array, with
  an address
• A memory address is an index to the array
  starting at 0
• Byte addressing means that the index points to a
  byte of memory

0 1 2 3
8 bit of data
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Memory organization

• Bytes are nice, but most data items use larger
  words
• For MIPS, a word is 32 bits or 4 bytes
• 232 bytes with byte address from 0 to 232-1
• 230 words with byte addresses 0,4,8, 232-4
• Words are aligned

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Addressing Objects Endinaness and Alignment

• Big Endian Address of most significant byteword
  address
• (xx00Big End of word)
• IBM 360/370 Motorola 68k, MIPS, Sparc, HP PA
• Little Endian address of least significant
  byteword address (xx00Little End of word)
• Intel 80x86, DEC VAX, DEC Alpha

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Continue
3
2
1
Little endian byte 0
0
msb
lsb
2
3
0
1
Big endian byte 0
0 1 2 3
aligned
Alignment require that objects fall on address
that is multiple of their size
Not aligned
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Operations in the instruction set

• the operators supported by most instruction set
  architectures can be characterized as follows
• Arithmetic and Logic Integer arithmetic and
  logical operations, add, and, subtract
• Data transfer Loads-store
• Control branch, jump, procedure call and return

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Continue

• system OS call, virtual memory management
  instruction
• decimal decimal add, decimal multiply
• floating point FP operations, add, multiply
• String string move, string compare, string
  search
• Graphics Pixel operations, compression and
  decompression operations

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Instruction for control flow

• measurements of branch and jump behavior are
  fairly independent of other measurements, we
  examine the use of control flows next
• there is no consistent name
• 1950s they called transfer
• 60s name branch began to be used
• Later, machines used additional name

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Top 10 instructions
Rank 80x86 instructions Integer
average total executed 1 load 22 2 con
ditional branch 20 3 compare 16 4 store
12 5 add 8 6 and 6 7 sub 5 8
move 4 9 call 1 10 return 1 total
96
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Type

• We can distinguish 4 different types of
  control-flow change
• 1. conditional branches
• 2. jumps
• 3. procedure calls
• 4. procedure returns

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figure
Integer average
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Call/return
Floating point average
11
6
Jump
4
81
Conditional branch
86
0
50
100
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conditional branches
integer
FP
75
lt, gt,
40
7
gt,lt,
23
86
Equal not equal
37
Comparison type in branches
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Instruction Cycle
Sequential execution model program is a sequence
of instructions Instructions are atomic and
executed seq Stored program concept program and
data both are stored in memory instruction are
fetched from memory for execution
Instruction fetch
Instruction decode
Operation fetch
execute
Result store
next