Lectures for 2nd Edition

1
CEG3151 Focus
Understanding the design techniques, machine
structures, technology factors, evaluation
methods for computer architectures
Assembly Language
Interface Design (ISA)
Technology
History
Compilers

• Computer Architecture
• Instruction Set Design
• Hardware/Software Boundary
• Architecture and Design
• Refinement for Performance

Measurement Evaluation
Memory
Processor Design - Data Path - Control
Parallelism
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Chapter 1
3
Introduction

• This course is all about how computers work
• But what do we mean by a computer?
• Different types desktop, servers, embedded
  devices
• Different uses automobiles, graphics, finance,
  genomics
• Different manufacturers Intel, Apple, IBM,
  Microsoft, Sun
• Different underlying technologies and different
  costs!
• Analogy Consider a course on automotive
  vehicles
• Many similarities from vehicle to vehicle (e.g.,
  wheels)
• Huge differences from vehicle to vehicle (e.g.,
  gas vs. electric)
• Best way to learn
• Focus on a specific instance and learn how it
  works
• While learning general principles and historical
  perspectives

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Why learn this stuff?

• You want to call yourself a computer scientist
• You want to build software people use (need
  performance)
• You need to make a purchasing decision or offer
  expert advice
• Both Hardware and Software affect performance
• Algorithm determines number of source-level
  statements
• Language/Compiler/Architecture determine machine
  instructions (Chapter 2 and 3)
• Processor/Memory determine how fast instructions
  are executed (Chapter 5, 6, and 7)
• Assessing and Understanding Performance in
  Chapter 4

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What is a computer?

• Components
• input (mouse, keyboard)
• output (display, printer)
• memory (disk drives, DRAM, SRAM, CD)
• network
• Our primary focus the processor (datapath and
  control)
• implemented using millions of transistors
• Impossible to understand by looking at each
  transistor
• We need...

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Abstraction

• Delving into the
• depths reveals more
• information
• An abstraction omits
• unneeded detail, helps us cope with
• complexityWhat are some of the
• details that appear in
• these familiar
• abstractions?

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Abstraction
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How do computers work?

• Need to understand abstractions such as
• Applications software
• Systems software
• Assembly Language
• Machine Language
• Architectural Issues i.e., Caches, Virtual
  Memory, Pipelining
• Sequential logic, finite state machines
• Combinational logic, arithmetic circuits
• Boolean logic, 1s and 0s
• Transistors used to build logic gates (CMOS)
• Semiconductors/Silicon used to build transistors
• Properties of atoms, electrons, and quantum
  dynamics
• So much to learn!

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Instruction Set Architecture

• A very important abstraction
• interface between hardware and low-level software
• standardizes instructions, machine language bit
  patterns, etc.
• advantage different implementations of the same
  architecture
• disadvantage sometimes prevents using new
  innovationsTrue or False Binary compatibility
  is extraordinarily important?
• Modern instruction set architectures
• IA-32, PowerPC, MIPS, SPARC, ARM, and others

10
Historical Perspective

• ENIAC built in World War II was the first general
  purpose computer
• Used for computing artillery firing tables
• 80 feet long by 8.5 feet high and several feet
  wide
• Each of the twenty 10 digit registers was 2 feet
  long
• Used 18,000 vacuum tubes
• Performed 1900 additions per second

• Since thenMoores Law transistor capacity
• doubles every
• 18-24 months

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Original

Big Fishes Eating Little Fishes
12
1988 Computer Food Chain
Mainframe
PC
Work- station
Mini- computer
Mini- supercomputer
Supercomputer

Massively Parallel Processors
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1998 Computer Food Chain
Mini- supercomputer
Mini- computer
Massively Parallel Processors

Mainframe
PC
Work- station
Server
Now who is eating whom?
Supercomputer
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Why Such Change in 10 years?
Performance Technology Advances CMOS VLSI
dominates older technologies (TTL, ECL) in cost
AND performance Computer architecture advances
improves low-end RISC, superscalar, RAID,
Price Lower costs due to Simpler
development CMOS VLSI smaller systems, fewer
components Higher volumes CMOS VLSI same dev.
cost 10,000 vs. 10,000,000 units Lower margins
by class of computer, due to fewer
services Function Rise of networking/local
interconnection technology

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Technology Trends Microprocessor Capacity
Alpha 21264 15 million Pentium Pro 5.5
million PowerPC 620 6.9 million Alpha 21164 9.3
million Sparc Ultra 5.2 million
Moores Law

• CMOS improvements
• Die size 2X every 3 yrs
• Line width halve / 7 yrs

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Memory Capacity (Single Chip DRAM)
year size(Mb) cyc time 1980 0.0625 250
ns 1983 0.25 220 ns 1986 1 190 ns 1989 4 165
ns 1992 16 145 ns 1996 64 120 ns 2000 256 100
ns

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Processor-DRAM Memory Gap (latency)
µProc 60/yr. (2X/1.5yr)
1000
CPU
Joys Law
100
Processor-Memory Performance Gap(grows 50 /
year)
Performance
10

DRAM 9/yr. (2X/10 yrs)
DRAM
1
1980
1981
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
1982
Time
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Chapter 2

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Technology Trends (Summary)
Capacity Speed (latency) Logic 2x in 3
years lt 2x in 3 years DRAM 4x in 3-4 years lt
2x in 10 years Disk 4x in 2-3 years lt 2x in
10 years

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Chapter 2

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Instructions

• Language of the Machine
• Well be working with the MIPS instruction set
  architecture
• similar to other architectures developed since
  the 1980's
• Almost 100 million MIPS processors manufactured
  in 2002
• used by NEC, Nintendo, Cisco, Silicon Graphics,
  Sony,

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MIPS arithmetic

• All instructions have 3 operands
• Operand order is fixed (destination
  first) Example C code a b c MIPS
  code add a, b, c (well talk about
  registers in a bit)The natural number of
  operands for an operation like addition is
  threerequiring every instruction to have exactly
  three operands, no more and no less, conforms to
  the philosophy of keeping the hardware simple

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MIPS arithmetic

• Design Principle simplicity favors regularity.
  
• Of course this complicates some things... C
  code a b c d MIPS code add a, b,
  c add a, a, d
• Operands must be registers, only 32 registers
  provided
• Each register contains 32 bits
• Design Principle smaller is faster. Why?

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Registers vs. Memory

• Arithmetic instructions operands must be
  registers, only 32 registers provided
• Compiler associates variables with registers
• What about programs with lots of variables

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Memory Organization

• Viewed as a large, single-dimension array, with
  an address.
• A memory address is an index into the array
• "Byte addressing" means that the index points to
  a byte of memory.

0
8 bits of data
1
8 bits of data
2
8 bits of data
3
8 bits of data
4
8 bits of data
5
8 bits of data
6
8 bits of data
...
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Memory Organization

• Bytes are nice, but most data items use larger
  "words"
• For MIPS, a word is 32 bits or 4 bytes.
• 232 bytes with byte addresses from 0 to 232-1
• 230 words with byte addresses 0, 4, 8, ... 232-4
• Words are aligned i.e., what are the least 2
  significant bits of a word address?

0
32 bits of data
4
32 bits of data
Registers hold 32 bits of data
8
32 bits of data
12
32 bits of data
...
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Instructions

• Load and store instructions
• Example C code A12 h A8 MIPS
  code lw t0, 32(s3) add t0, s2, t0 sw
  t0, 48(s3)
• Can refer to registers by name (e.g., s2, t2)
  instead of number
• Store word has destination last
• Remember arithmetic operands are registers, not
  memory! Cant write add 48(s3), s2,
  32(s3)

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Our First Example

• Can we figure out the code?

swap(int v, int k) int temp temp
vk vk vk1 vk1 temp
swap muli 2, 5, 4 add 2, 4, 2 lw
15, 0(2) lw 16, 4(2) sw 16, 0(2)
sw 15, 4(2) jr 31
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So far weve learned

• MIPS loading words but addressing bytes
  arithmetic on registers only
• Instruction Meaningadd s1, s2, s3 s1
  s2 s3sub s1, s2, s3 s1 s2 s3lw
  s1, 100(s2) s1 Memorys2100 sw s1,
  100(s2) Memorys2100 s1

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Instruction Formats

Variable Fixed Hybrid

• Addressing modes
• each operand requires addess specifier gt
  variable format
• code size gt variable length instructions
• performance gt fixed length instructions
• simple decoding, predictable operations
• With load/store instruction arch, only one memory
  address and few addressing modes
• gt simple format, address mode given by opcode

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Review Basic Instruction Classes

• Accumulator
• 1 address add A acc ? acc memA
• 1x address addx A acc ? acc memA x
• Stack
• 0 address add TOTS ? TOTS next
• EA to EA
• 2 address add A, B EA(A) ? EA(A) EA(B)
• 3 address add A, B, C EA(A) ? EA(B)
  EA(C)
• Load/Store
• 3 reg add Ra, Rb, Rc Ra ? Rb Rc
• load Ra, Rb Ra ? memRb
• store Ra, Rb memRb ? Ra

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MIPS R3000 (Microprocessor without Interlock
Pipeline Stage)
0
r0 r1 r31
Programmable storage 232 x bytes 31 x 32-bit
GPRs (R00) 32 x 32-bit FP regs (paired DP) HI,
LO, PC
Data types ? Format ? Addressing Modes?
PC lo hi
Arithmetic logical Add, AddU, Sub, SubU,
And, Or, Xor, Nor, SLT, SLTU, AddI, AddIU,
SLTI, SLTIU, AndI, OrI, XorI, LUI. SLL, SRL, SRA,
SLLV, SRLV, SRAV Memory Access LB, LBU, LH, LHU,
LW, LWL,LWR, SB, SH, SW, SWL, SWR Control J,
JAL, JR, JALR, BEQ, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZA
L,BGEZAL
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MIPS, ISA Registers
Register 1 (at) reserved for assembler, 26-27
for operating system
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Machine Language

• Instructions, like registers and words of data,
  are also 32 bits long
• Example add t1, s1, s2
• registers have numbers t19, s117, s218
• add 9, 17, 18
• rd rs rt
• Instruction Format 000000 10001 10010 01001 000
  00 100000 op rs rt rd shamt funct
• Machine Code 02 32 48 20h
• Can you guess what the field names stand for?

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Machine Language

• Consider the load-word and store-word
  instructions,
• What would the regularity principle have us do?
• New principle Good design demands a compromise
• Introduce a new type of instruction format
• I-type for data transfer instructions
• other format was R-type for register
• Example lw t0, 41(s2) 35 18 8
  41 op rs rt 16 bit number
• Where's the compromise? Displacement limit. Can
  be -

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Stored Program Concept

• Instructions are bits
• Programs are stored in memory to be read or
  written just like data
• Fetch Execute Cycle
• Instructions are fetched and put into a special
  register
• Bits in the register "control" the subsequent
  actions
• Fetch the next instruction and continue

memory for data, programs, compilers, editors,
etc.
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Control

• Decision making instructions
• alter the control flow,
• i.e., change the "next" instruction to be
  executed
• MIPS conditional branch instructions bne t0,
  t1, Label1 beq t0, t1, Label2
• Example if (ij) h i j bne s0, s1,
  Label add s3, s0, s1 Label ....

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Control

• MIPS unconditional branch instructions j label
• Example if (i!j) beq s4, s5, Lab1
  hij add s3, s4, s5 else j Lab2
  hi-j Lab1 sub s3, s4, s5 Lab2
  ...
• Can you build a simple for loop? Yes..

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So far

• Instruction Meaningadd s1,s2,s3 s1 s2
  s3sub s1,s2,s3 s1 s2 s3lw
  s1,100(s2) s1 Memorys2100 sw
  s1,100(s2) Memorys2100 s1bne
  s4,s5,L Next instr. is at Label if s4 ?
  s5beq s4,s5,L Next instr. is at Label if
  s4 s5j Label Next instr. is at Label
• Formats

R I J
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Control Flow

• We have beq, bne, what about Branch-if-less-than
  ?
• New instructionSet On Less Than if s1 lt s2
  then t0 1slt t0, s1, s2 else
  t0 0
• Can use this instruction to build "blt s1, s2,
  Label" can now build general control
  structures
• Note that the assembler needs a register to do
  this, there are policy of use conventions for
  registers

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Constants

• Small constants are used quite frequently (50 of
  operands) e.g., A A 5 B B 1 C
  C - 18
• Solutions? Why not?
• put 'typical constants' in memory and load them.
  
• create hard-wired registers (like zero) for
  constants like one.
• MIPS Instructions addi 29, 29, 4 slti 8,
  18, 10 andi 29, 29, 6 ori 29, 29, 4
• Design Principle Make the common case fast.
  Which format?

42
How about larger constants?

• We'd like to be able to load a 32 bit constant
  into a register
• Must use two instructions, new "load upper
  immediate" instruction lui t0,
  1010101010101010
• Then must get the lower order bits right,
  i.e., ori t0, t0, 1010101010101010

1010101010101010
0000000000000000
0000000000000000
1010101010101010
ori
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Assembly Language vs. Machine Language

• Assembly provides convenient symbolic
  representation
• much easier than writing down numbers
• e.g., destination first
• Machine language is the underlying reality
• e.g., destination is no longer first
• Assembly can provide 'pseudoinstructions'
• e.g., move t0, t1 exists only in Assembly
• would be implemented using add t0,t1,zero
• When considering performance you should count
  real instructions

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Other Issues

• Discussed in your assembly language programming
  lab support for procedures linkers, loaders,
  memory layout stacks, frames, recursion manipula
  ting strings and pointers interrupts and
  exceptions system calls and conventions
• Some of these we'll talk more about later
• Well talk about compiler optimizations when we
  hit chapter 4.

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Overview of MIPS

• simple instructions all 32 bits wide
• very structured, no unnecessary baggage
• only three instruction formats
• rely on compiler to achieve performance what
  are the compiler's goals?
• help compiler where we can

op rs rt rd shamt funct
R I J
op rs rt 16 bit address
op 26 bit address
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Addresses in Branches and Jumps

• Instructions
• bne t4,t5,Label Next instruction is at Label
  if t4 / t5
• beq t4,t5,Label Next instruction is at Label
  if t4 t5
• j Label Next instruction is at
  Label
• Formats
• Addresses are not 32 bits How do we handle
  this with load and store instructions?

op rs rt 16 bit address
I J
op 26 bit address
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Addresses in Branches

• Instructions
• bne t4,t5,Label Next instruction is at Label
  if t4?t5
• beq t4,t5,Label Next instruction is at Label
  if t4t5
• Formats
• Could specify a register (like lw and sw) and add
  it to address
• use Instruction Address Register (PC program
  counter)
• most branches are local (principle of locality)
• Jump instructions just use high order bits of PC
• address boundaries of 256 MB

op rs rt 16 bit address
I
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To summarize
49
To summarize
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MIPS Addressing Modes Formats

• Simple addressing modes
• All instructions 32 bits wide

Register (direct)
op
rs
rt
rd
register
Immediate
immed
op
rs
rt
Baseindex
immed
op
rs
rt
Memory
register

PC-relative
immed
op
rs
rt
Memory
PC

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Alternative Architectures

• Design alternative
• provide more powerful operations
• goal is to reduce number of instructions executed
• danger is a slower cycle time and/or a higher
  CPI
• Lets look (briefly) at IA-32

The path toward operation complexity is thus
fraught with peril. To avoid these problems,
designers have moved toward simpler instructions
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IA - 32

• 1978 The Intel 8086 is announced (16 bit
  architecture)
• 1980 The 8087 floating point coprocessor is
  added
• 1982 The 80286 increases address space to 24
  bits, instructions
• 1985 The 80386 extends to 32 bits, new
  addressing modes
• 1989-1995 The 80486, Pentium, Pentium Pro add a
  few instructions (mostly designed for higher
  performance)
• 1997 57 new MMX instructions are added,
  Pentium II
• 1999 The Pentium III added another 70
  instructions (SSE)
• 2001 Another 144 instructions (SSE2)
• 2003 AMD extends the architecture to increase
  address space to 64 bits, widens all registers
  to 64 bits and other changes (AMD64)
• 2004 Intel capitulates and embraces AMD64
  (calls it EM64T) and adds more media extensions
• This history illustrates the impact of the
  golden handcuffs of compatibilityadding new
  features as someone might add clothing to a
  packed bagan architecture that is difficult
  to explain and impossible to love

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IA-32 Overview

• Complexity
• Instructions from 1 to 17 bytes long
• one operand must act as both a source and
  destination
• one operand can come from memory
• complex addressing modes e.g., base or scaled
  index with 8 or 32 bit displacement
• Saving grace
• the most frequently used instructions are not too
  difficult to build
• compilers avoid the portions of the architecture
  that are slow
• what the 80x86 lacks in style is made up in
  quantity, making it beautiful from the right
  perspective

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IA-32 Registers and Data Addressing
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IA-32 Register Restrictions

• Registers are not general purpose note the
  restrictions below

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IA-32 Typical Instructions

• Four major types of integer instructions
• Data movement including move, push, pop
• Arithmetic and logical (destination register or
  memory)
• Control flow (use of condition codes / flags )
• String instructions, including string move and
  string compare

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IA-32 instruction Formats

• Typical formats (notice the different lengths)

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Summary

• Instruction complexity is only one variable
• lower instruction count vs. higher CPI / lower
  clock rate
• Design Principles
• simplicity favors regularity
• smaller is faster
• good design demands compromise
• make the common case fast
• Instruction set architecture
• a very important abstraction indeed!