Virtual Memory

1
Virtual Memory

• So, what happens when we can only load part of a
  program into memory?
• Well, we can still run a program since we only
  need to have the parts of the program that are
  currently in use in memory. This is the basic
  theory behind virtual memory.
• Can we extend this concept to multiprogramming?

2
Virtual Memory through Paging

• Our programs are capable of generating memory
  addresses, but these addresses usually differ
  (may span a larger range) from actual memory.
• The program generated addresses are called
  virtual addresses.

3
Mapping of Virtual to Physical Memory via MMU
4
How do we fit virtual memory onto physical memory?

• Virtual memory can be divided up into equal size
  units called pages.
• We can also divide the physical memory into sizes
  that would accommodate a single page called a
  page frame.

5
Virtual vs. Physical Memory
Processor can generate 16-bit addresses. How
much memory can we address with 16 bits? We only
have 32K of Physical Memory. Job of the MMU to
map the virtual address to the physical. Why may
processors designed for embedded systems not have
an MMU on the CPU?
6
What happens when our page is not mapped?

• When we try to reference a page that is currently
  not mapped onto physical memory a page fault is
  generated.
• A page must be evicted (stored back on disk) from
  physical memory.
• Evicted page must be marked as not mapped.
• New page must be loaded and mapped.

7
How do we actually translate a virtual address to
physical?
MMU performs the mapping of virtual to physical
by means of a page table lookup. How many bits
are needed to specify 16 different pages? How
many bits are needed to specify 8 page frames?
page_table(virtual address) physical address
8
Consider theses Page Table Issues

• Processor capable of generating 32 bit addresses.
• How many pages we would have assuming 4KB page
  sizes?
• Obviously our page table can be very large.
• The mapping must be fast since it is done upon
  each memory reference

9
2 Extremes of Page Table Design

• Use hardware registers for each virtual page.
• Requires no memory references during mapping
  since all mappings can be calculated from the
  table
• Obviously expensive to implement with large
  tables
• Keep the page table in memory and have a single
  register that points to the page table
• Only requires 1 register to be updated with each
  process switch
• Must go out to memory to read the table entries

10
Real World Implementation for Page Tables

• Use of Multi-level pages.
• Basically each level allows for indexing into a
  more specific block of memory than the previous
  level.

11
Multi-Level Page Table
32-bit addresses that use the upper 20 bits for
indexing to 2 levels of page tables. How many
virtual pages can we have? How does the MMU look
at resolving the physical address? How many page
tables are actually needed in this example?
12
Examine a single page table entry
13
TLB Translation Lookaside Buffers

• Even though a multilevel paging system seems to
  be great for quickly resolving a physical memory
  references we must still load the page tables
  from memory.
• This can result in a big performance hit.
• TLBs can be used to provide quick physical
  address resolution by exploiting the principle of
  locality.

14
Check the TLB first

• On many machines TLBs are put in place so that
  they can be check first before going to load a
  page table.
• Usually part of the processor MMU
• MMU does the comparison of all entries in the TLB
  to find a virtual address in parallel.

15
Example of a TLB
The TLB entries look the same as what we find in
a page table.