CSC%206001%20VLSI%20CAD%20(Physical%20Design)

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CSC 6001VLSI CAD (Physical Design)

• January 23 2006

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Graph-based Representation of Boolean Functions

• Graph Based Algorithms for Boolean Function
  Manipulation, Randal E. Bryant, IEEE
  Transactions on Computers, Vol C-35, No. 8, 1986

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Motivation

• If you have 2 boolean functions
• f(x1, x2, , xk) and g(x1, x2, , xk)
• How do you know if they represent the same
  function?

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Motivation
g(x1, x2, , xk)
f(x1, x2, , xk)
Gg
Gf
Then we can compare graph Gf and Gg. What
properties should these graphs have for easy
comparison?
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Motivation

• We want the graph representation to be
• Unique for each boolean function.
• Can be operated on just like the boolean
  functions.

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Ordered BDD

• A data structure to represent boolean function.
• Directed acyclic graph (DAG)
• Only one root node and two terminal nodes.
• One terminal node labeled 0 and the other 1.
• All non-terminal nodes are labeled with variable
  names.

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Ordered BDD
This represents the function
a
a1
a0
f ab c
b
c
b0
b1
c0
c1
1
0
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Ordered BDD

• Every internal node has 2 successors.
• Ordered means that if x lt y, then all nodes
  labeled x precede all nodes labeled y in the BDD.
• From now onwards, we will label the non-terminals
  with the orders of the variables only.

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Examples
1
1
0
1
1
0
2
2
1
1
0
0
0
1
3
3


What are these functions?
0
1
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Notations
index(v)
1
1
non-terminal
low(v)
0
2
v
3
0
high(v)
1
0
1
value(u)
terminal
1
0
u
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BDD ? Boolean Function

• For each node v, the subgraph rooted at v
  represents a function fv defined recursively as
  follow
• If v is a terminal node
• If value(v) 1, then fv 1.
• If value(v) 0, then fv 0.
• Else, v is a non-terminal with index(v) i
• fv(x1, , xn) xi f low(v) (x1, , xn)
• xi f high(v) (x1, , xn)

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Example
1
1
0
2
3
0
What boolean function does it represent?
1
1
4
0
0
1
1
0
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Reduced BDD

• A BDD is reduced if it contains no
• node v with low(v) high(v), nor
• distinct nodes v and v such that he subgraphs
  rooted at v and v are identical.

1
1
0
How to reduce this BDD?
2
2
1
1
0
0
3
3
1
1
0
0
1
0
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Uniqueness of Reduced BDD

• Theorem For any boolean function f(x1, , xn),
  there is a unique reduced BDD representing f with
  variable ordering x1lt lt xn.

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Ordering Dependency
1
1
0
2
What is this function?
3
1
1
0
What if we change the order to 1 ? 3 ? 5 ? 2 ? 4
? 6
4
0
1
5
1
6
0
1
0
1
0
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Ordering Dependency

• Consider x1xn1 xnx2n
• fb1,bn(xn1, , x2n) b1xn1 bnx2n
• For all 2n possible combinations of the values
  b1, , bn, each of these functions is distinct
  and they must be represented by distinct
  subgraphs in the BDD. Therefore, there exists at
  least 2n nodes in the reduced BDD.

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Inherently Complex Functions

• Integer multiplier
• Input a1, , an and b1, , bn
• Output c1, , c2n representing the integer a?b.
• Theorem For any ordering of the inputs, at least
  one of the 2n functions for c1, , c2n requires a
  graph containing at least 2n/8 nodes.

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Circuit Partitioning by Network Flow Approach

• Efficient Network Flow Based Min-Cut Balance
  Partitioning, Yang and Wong, ICCAD, pp.50-55,
  1994.

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k-Way Partitioning

• Problem Formulation
• Given a netlist of n cells V v1, v2, , vn,
  assign the cells to k clusters Pk C1, C2, ,
  Ck satisfying some given constraints such that
  an objective function F(Pk) is optimized.
• Partitioning k is small O(1)
• Clustering k is large O(n)
• Technology Mapping Constraints on the clusters.

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Network Flow Technique
12/12
12
b
b
a
a
20
19/20
11/16
16
s
t
s
t
10
4
9
7
10
1/4
9
7/7
13
4
12/13
4/4
c
d
c
d
11
11/11
min-cut max-flow
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Network Flow Technique

• The network flow technique can find the min-cut
  bipartition optimally, but not necessarily
  balanced.
• Apply the algorithm repeatedly to obtain a
  balanced bipartition.

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Network Flow Technique

• The network flow technique is very useful in
  different research areas.
• Many sophisticated improvements have been made to
  the original algorithm.
• Edmonds-Karp O(VE2)
• Ford Fulkerson O(Ef) where f is the size
  of the total flow. Note that for unit capacity,
  f ? E, so O(E2) time.

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Circuit Partitioning

• We can apply the network flow algorithm in
  partitioning circuits.
• The biggest problem is that the two partitions
  may not be balanced.
• The problem of obtaining two balanced partitions
  with minimum cut is NP-complete.
• However we can apply some heuristics to balance
  the two partitions.

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Flow-Balanced-Bipartition (FBB)

• Find a min-cut C (X,Y) in the network N.
• If (1-?)W/2 ? w(X) ? (1?)W/2, stop and return C.
• If w(X) lt (1-?)W/2 then
• Collapse all nodes in X to s.
• Collapse to s a node v?Y incident on a net in C.
• Goto to step 1.
• If w(X) gt (1?)W/2 (similarly) ...

Why do we need this step?
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Circuit Representation

• Another problem in applying the network flow
  technique in circuit partitioning is how to
  represent a circuit correctly by a graph.

A
B
C
D
How to represent this netlist by a simple graph?
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Hypergraph
In hypergraph, an edge is a set of vertices.
H(V,E) where V A, B, C, D E n1, n2, n3 n1
A, B, C, D n2 A, B n3 C, D
A
B
C
D
Circuits can be represented by hypergraphs, but
the net-work flow method can only be used in
simple graphs.
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Circuit Representation

• Use a clique to model a net

A
B
C
D
What should be the edge weights?
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Circuit Representation
Cut size 41/4 1 (Actual cut
size 1)
1/4
Cut size 31/41/2 5/4 (Actual cut
size 2)
1/4
1/4
1/4
1/4
1/4
n(k) no. of cells in net k
A
B
C
D
1/2
1/2
edge weight
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Circuit Representation
Cut size 41/3 4/3 (Actual cut
size 1)
1/3
Cut size 31/31 2 (Actual cut size
2)
1/3
1/3
1/3
1/3
1/3
A
B
C
D
1
1
edge weight
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Circuit Representation

• It is proved that exact modeling of a hyper-graph
  by a graph with positive weights is impossible.
  Ihler, Wagner Wager, 1993
• However, we can model a hypergraph H by a simple
  graph G such that when we apply the network flow
  algorithm, the min-cut in G is equal to the
  min-cut in H.

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Circuit Representation
Original circuit C
G
B
B
?
?
?
A
A
?
1
?
C
?
C
What will happen when we apply the max-flow
min-cut algorithm to the graph G?
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Circuit Representation
1
?
?
?
?
?
?
?
?
A
B
C
D
?
?
?
?
?
?
?
?
1
1
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Modeling a Circuit
C
G
d
b
d
b
a
e
g
s
e
t
c
f
c
f
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Modeling a Circuit

• Lemma If C has a cut (X,Y) of size K, G has a
  cut (X,Y) of size K. If G has a cut (X,Y) of
  size K, C has a cut (X,Y) of size less than or
  equal to K.
• Corollary If (X,Y) is the min-cut of G of size
  K, the corresponding cut (X,Y) in C is also a
  min-cut of C of size K.