Ion Mandoiu

1
Challenges in Design Automation for Nanoscale
VLSI and DNA Systems

• Ion Mandoiu
• ECE Department, UC San Diego

2
Outline

• Challenges for nanoscale VLSI design
• New algorithmic framework for global interconnect
  synthesis
• New methodology for redundant interconnect
• Future research directions in VLSI and DNA design
  automation

• Challenges for nanoscale VLSI design
• New algorithmic framework for global interconnect
  synthesis
• New methodology for redundant interconnect
• Future research directions in VLSI and DNA design
  automation

3
Historical Trends in VLSI Scaling

• Exponential integration rate (Moores Law)

• Exponential decrease in cost/transistor

• Tremendous economic impact

4
Will these trends continue?

• Exponential integration rate expected to continue
  for 1-2 decades
• Moore 2003 No exponential is forever but we can
  delay forever

5
Will these trends continue?

• Exponential integration rate expected to continue
  for 1-2 decades
• Moore 2003 No exponential is forever but we can
  delay forever
• International Technology Roadmap for
  Semiconductors (ITRS)
• 800 experts from industry, academia, governments
  worldwide
• Sets targets for RD needs over 15 year horizon

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ITRS 2001 targets

• Dynamic Random Access Memory ½ Pitch 22 nm by
  2016

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ITRS 2001 targets

• Dynamic Random Access Memory ½ Pitch 22 nm by
  2016

• Physical gate length 9 nm by 2016

Production Year
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Nanoscale Integration Challenges
2.2 billion trans./cm2 by 2016!

• System complexity

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Nanoscale Integration Challenges
Global interconnect gets slower

• System complexity

• Timing closure

Repeaters help
Local interconnect gates get faster
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Nanoscale Integration Challenges

• System complexity

• Timing closure

• Signal integrity
• Power consumption
• Manufacturing reliability
• Verification and test
• Manufacturing cost

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Implications for Nanoscale Design

• Challenges must be addressed at all design phases
• - Flow integration, early planning

• Need new methodologies
• - Interconnect-centric design, design for test,
  design for manufacturing
• ? Need improved optimization algorithms
• - Highly scalable, predictable solution quality

12
Outline

• Challenges for nanoscale VLSI design
• New algorithmic framework for global interconnect
  synthesis
• New methodology for redundant interconnect
• Future research directions in VLSI and DNA design
  automation

13
Nanoscale VLSI Context

• Timing closure signal integrity require
• Aggressive optimizations
• Buffer insertion
• Buffer sizing
• Pin assignment
• Wire sizing
• Simultaneous control of
• Routing resources
• Congestion
• Power consumption
• Need predictable scalable integrated approach
• 106 buffers / die in 50nm technology

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Buffer Planning Methodologies
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Buffer Planning Methodologies
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Global Buffered Routing Framework

• Tile graph model ? captures routing/buffer
  congestion

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Global Buffered Routing Framework

• Tile graph model ? captures routing/buffer
  congestion

• Problem formulation

• Given
• Tile graph G with
• wire capacity w(u,v) routing channels
  between tile u and v
• buffer capacity b(v) buffers sites in
  tile v
• Netlist (2-pin nets)
• Maximum buffer load U (in tiles)

Find Feasible buffered routing minimizing total
routing area ?(buffers) ?(total wirelength)
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Global Buffered Routing Framework

• Tile graph model ? captures routing/buffer
  congestion

• Reformulation as integer multicommodity flow
  problem

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Global Buffered Routing Framework

• Tile graph model ? captures routing/buffer
  congestion

• Reformulation as integer multicommodity flow
  problem

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Global Buffered Routing Framework

• Tile graph model ? captures routing/buffer
  congestion

• Reformulation as integer multicommodity flow
  problem

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Global Buffered Routing Framework

• Tile graph model ? captures routing/buffer
  congestion

• Reformulation as integer multicommodity flow
  problem

• RelaxRound approach
• Provably good solution quality RaghavanT87
• Key to runtime scalability approximate solution
  to the fractional relaxation
• Generalizes edge-capacitated MCF approximation of
  GargK98, F99

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High-Level Algorithm Idea

• Iteratively construct both primal and dual
  solutions
• In each phase, route one unit of flow for each
  commodity
• Flow routed along min-weight path w.r.t. dual
  variables (using Dijkstra)
• Dual variables for vertices/edges on routed path
  are scaled by a multiplicative factor
• ? Exponential dependence on usage (often used
  vertices/edges subsequently avoided)

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Extensions

• Pin assignment
• Buffer sizing
• Wire sizing
• Layer assignment
• Sink delay upper bounds (Elmore-Delay)
• - delay constrained min-weight paths
• Multi-pin nets

• Simultaneous optimization!

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Experimental Results
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Experimental Results
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Experimental Results
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Global Interconnect Summary

• Powerful algorithmic framework based on
  multicommodity flows
• Simultaneous consideration of wire and buffer
  congestion, pin layer assignment, sizing,
  timing constraints
• Flexible tradeoff between runtime and solution
  quality

• Ongoing work
• Further improvements in algorithm scalability
• Window vs. tile buffer constraints

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Outline

• Challenges for nanoscale VLSI design
• New algorithmic framework for global interconnect
  synthesis
• New methodology for redundant interconnect
• Future research directions in VLSI and DNA design
  automation

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Trends in Manufacturing Reliability

• Defects difficult to control in nanoscale
  processes
• Interconnect defects increasingly dominant

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Previous Work

• Focused on reduction of short faults
• Conservative design rules
• Decompaction
• Routing for reliable manufacturing
• DTR Defect Tolerant Routing (Pitaksanonkul et
  al. 1985)
• YOR Yield Optimizing Routing (Kuo 1993)
• Reliability-aware routing costs
  (Huijbregts,XueJess 1995)
• Open faults become dominant due to change from
  aluminum to copper interconnect
• - Aluminum is etched ? short faults
• - Copper is deposited ? open faults

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POF Opens vs. Shorts

• Open faults are significantly (3x) more likely to
  occur

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Techniques for Open POF Reduction

• Wire doubling
• Redundant interconnect
• Easy to integrate in current flows
  (post-processing approach)
• Potentially more effective use of resources
• How effective?

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Problem Formulation

• Manhattan Routed Tree Augmentation Problem
• Given
• Tree T routed in the Manhattan plane
• Feasible routing region
• Wirelength increase budget W
• Find
• Augmenting paths A within feasible region
• Such that
• Total length of augmenting paths is less than W
• Total length of biconnected edges in T?A is
  maximum

• Wirelength increase budget used to balance open
  POF decrease with short POF increase

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Types of Allowed Augmenting Paths
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Integer Linear Program (Type A-C Paths)

• 
  Total biconnected length
• Subject to
• 
  Wirelength budget
• 
  (u,v) biconnected if some p connects Tu Tv
• 
  pxp1 gives augmenting paths
• 
  eye1 gives biconnected tree edges

P set of -- at most O(n2) -- augmenting paths
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Integer Linear Program (Type A-C Paths)

• 
  Total biconnected length
• Subject to
• 
  Wirelength budget
• 
  (u,v) biconnected if some p connects Tu Tv
• 
  pxp1 gives augmenting paths
• 
  eye1 gives biconnected tree edges

P set of -- at most O(n2) -- augmenting paths
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Empirical Evaluation

• Compared algorithms
• Integer program solved using CPLEX
• Greedy augmentation algorithm
• Best-drop heuristic (Khuller-Raghavachari-Zhu
  99)
• Recent genetic algorithm (Raidl-Ljubic 2002)
• Test Cases
• Random nets nets extracted from real designs
• No routing obstacles

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Biconnectivity-Wirelength Tradeoff
Random 20-terminal nets
? 68 biconnectivity with 20 WL increase
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Max SPICE Delay (ps)

• 52-56 terminal nets, routed for min-area

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Max SPICE Delay (ps)

• 52-56 terminal nets, routed for min-area

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Max SPICE Delay (ps)

• 52-56 terminal nets, routed for min-area

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Max SPICE Delay (ps)

• 52-56 terminal nets, routed for min-area

• Redundant interconnect improves max delay
• 28 average, 62 max. improvement for 20 WL
  increase

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Redundant Interconnect Summary

• New methodology for redundant interconnect
  synthesis
• Easy to integrate in current flows
• Significant biconnectivity increase with small
  increase in wirelength

• Ongoing work
• Multiple net augmentation
• Simultaneous tree augmentation and decompaction
• Reliability with timing constraints

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Outline

• Challenges for nanoscale VLSI design
• New algorithmic framework for global interconnect
  synthesis
• New methodology for redundant interconnect
• Future research directions in VLSI and DNA design
  automation

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Ongoing and Future Research Directions

• VLSI Design Automation
• Physical design (non-Manhattan interconnect
  architectures, clock synthesis,)
• Design for test, built-in self-test
• Design for manufacturing, cost optimizations
  (multi-project wafers, reduced-field reticles)
• Sensor and Ad Hoc Wireless Networks
• Broadcasting and routing protocols
• Power consumption
• DNA Array Design Automation
• Scalable tools for next-generation DNA arrays
• Enhanced Design Flow

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DNA Probe Arrays

• Introduced in early 90s
• Short DNA probes that hybridize to unknown
  genetic material
• Used in gene expression monitoring, mutation
  detection, single nucleotide polymorphism (SNP)
  analysis, medical diagnosis

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DNA Array Manufacturing Process
Very Large Scale Imobilized Polymer Synthesis
(VLSIPS)
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Technology Scaling Challenges

• 1,000x1,000 arrays in commercial production
  today
• 10,000x10,000 array sites in next generation
• Scaling effects increased unwanted illumination

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Example Probe Synthesis
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Measure of Unwanted Illumination
Unwanted illumination ? border length
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Synchronous Synthesis

• Periodic deposition sequence, e.g., (ACTG)k

• Probes grow in sync, one nucleotide per period

? Border length 2 x Hamming distance
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2-D Placement Problem(Synchronous Synthesis)
Edge cost 2 x Hamming dist
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Previous Approaches

• Hubbell 90s
• Find TSP w.r.t. Hamming dist
• Thread TSP to grid row by row

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Highly-Scalable 2-D Placement

• Sorting Threading

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Highly-Scalable 2-D Placement

• Sorting Threading

• Sliding-Window Matching

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Highly-Scalable 2-D Placement

• Sorting Threading

• Sliding-Window Matching

• Epitaxial placement
• Simulates crystal growth
• Efficient tile row versions

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Asynchronous Synthesis

• Arbitrary deposition sequence
• Probes grow at different speeds

• Border depends on embeddings into deposition
  sequence
• ? 3-D placement problem

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Optimal Probe Embedding

• Dynamic programming algorithm similar to LCS

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3-D Placement Algorithms

• Simultaneous placement and alignment
  (asynchronous epitaxial)
• Slow, poor solution quality
• Synchronous placement iterative probe embedding
  
• Scalable, better solution quality
• Synchronous placement asynchronous sliding
  window matching
• Scalable, best solution quality

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DNA Arrays Summary

• Experimental flow with fully scalable components
  improves border length by 5 over industry
  designs

• Ongoing and future work
• Integrated DNA array flow
• Lab-on-chip sensors

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Thank You for Your Attention!