AnalogtoDigital Converters

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Analog-to-Digital Converters

• Jaehyun Lim
• Department of Computer Science and Engineering
• The Pennsylvania State University

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ADC Glossary

• DNL (differential nonlinearity)
• measure of the maximum deviation from the ideal
  step size of 1 LSB

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ADC Glossary

• INL (integral nonlinearity)
• deviation of the entire transfer function from
  the ideal function

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ADC Glossary

• Offset Error
• difference between the ideal LSB transition to
  the actual transition point

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ADC Glossary

• Gain Error
• how well the slope of the actual transfer
  function matches the slope of the ideal transfer
  function

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ADC Glossary

• Resolution
• number of discrete values it can produce
• Monotonic
• digital output code always increases as the ADC
  analog input increases
• Full scale
• voltage range ADC can accept
• Aliasing
• due to unwanted signals beyond the Nyquist limit
• to prevent, all undesired signals must be
  filtered

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ADC Glossary

• SINAD (signal-to-noise and distortion)
• RMS value of the output signal to the RMS value
  of all of the other spectral components below
  half the clock frequency
• ENOB (effective number of bits)
• dynamic performance of an ADC at a specific input
  frequency and sampling rate

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High Speed ADC Architecture

• Flash ADC
• highest speed
• large of comparators
• large size
• large power consumption
• 8-bit maximum resolution

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High Speed ADC Architecture

• Two-Step Flash ADC
• SHA
• D/A converter
• subtractor
• coarse flash ADC (MSB)
• find flash ADC (LSB)
• reduce of comparators
• 2N-1 2(2N/2-1)

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High Speed ADC Architecture

• Pipelined ADC
• multi-stage conversion
• high speed
• acceptable power
• each stage has SHA, ADC, DAC, subtractor, Amp
• different conversion step concurrently

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High Speed ADC Architecture

• Folding ADC
• no SHA (flash)
• reduce of comparators
• (two step flash)
• small area, high speed
• rounding problem

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High Speed ADC Architecture

• Time-Interleaved ADC
• multiple ADCs in parallel high speed
• offset/gain mismatch
• phase skew

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And More ADC Architectures

• Algorithmic ADC
• low power, small size, slow
• Integrating-Type ADC
• high accuracy, simple architecture, very slow
• Successive Approximation ADC
• RC / CR Type ADC
• Interpolating ADC

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Design Consideration Flash ADC

• Large Input Capacitance
• parallel structure of 2N-1 comparators
• limits speed performance
• large size buffer
• Bubble / Sparkle
• no SHA, comparator mismatch
• error in thermometer code
• solution 3-input NAND

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Design Consideration Flash ADC

• Metastability
• input to ADC comparator reference
• indeterminate output error
• solution latch pipelining (extra gain)
• gray encoding (no signal
  split)

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Design Consideration Flash ADC

• Clock Distribution and Timing
• clock travels long distance on a large ADC chip
• different delay, different loading
• Kickback Noise
• disturbs reference

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Design Consideration Two-Step Flash ADC

• Subtractor Gain
• without gain stage
• output of subtractor 1-LSB of coarse ADC
• difficult comparator design
• (offset lt 1-LSB of fine ADC)
• with gain stage
• delay
• mismatch between subtractor output and fine ADC
  input full scale
• missing code / nonmonotonicity

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Design Consideration Two-Step Flash ADC

• Nonlinearity
• SHA

residue
residue
including errors

• gain mismatch
• DNL, INL
• offset
• ...

Vin
Vin
analog
input
level sensed by subtractor
?V
level digitized by coarse ADC
t
t1
t2
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Design Consideration Pipelined Flash ADC

• MDAC (Multiplying D/A Converter)
• - performs subtractor, gain amplifier, S/H, and
  DAC

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Design Consideration Pipelined Flash ADC

• MDAC Operation

removes offset
Vx
(2N-1)CVin

CVin
Qi


2NCVin
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Design Consideration Pipelined Flash ADC

• MDAC Operation

Qf 2NCDVref CVo from QinQf, Vo
2N(Vin-DVref)
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Design Consideration Folding ADC

• Rounding Problem
• - only linear at zero-crossings

limits resolution to 10 bits
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Design Consideration Folding ADC

• Multiple Folds

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Two-Step Flash ADC Implementation

• SHA
• 4-bit Coarse ADC
• 3-bit Fine ADC
• Resistor-String DAC
• Voltage Subtractor
• Amplifier
• Registers

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Two-Step Flash ADC Implementation

• Coarse ADC

Fat-Tree Encoder
Bubble Correction
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Two-Step Flash ADC Implementation

• Coarse ADC

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Two-Step Flash ADC Implementation

• Resistor-String DAC
• voltage scaling DAC
• simple
• fast
• small (under 8-bit)
• resistor mismatching

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Two-Step Flash ADC Implementation

• Resistor-String DAC

0001
1111
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Two-Step Flash ADC Implementation

• SHA

input
output
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Two-Step Flash ADC Implementation

• Voltage Subtractor

V2
8 x (V1-V2)
V1
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Two-Step Flash ADC Implementation

• Things To Be Done
• voltage subtractor and gain amplifier
• - input voltage range for the subtractor
• - output offset
• - proper gain setting (input range of fine ADC)
• 3-bit fine ADC
• - identical to the 4-bit coarse ADC