State Machines

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Lecture 5

• State Machines

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Agenda

• Lab 4 Quick Review
• State Machines
• Inference / functionality
• Hazards (illegal states)

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Types / Operators 4 Rules

• Unsigned, signed are arrays of std_logic (just
  like Std_Logic_Vector)
• use closely related type conversion functions to
  convert between above
• My_slv lt std_logic_vector(my_unsigned)
• My_unsigned lt unsigned(my_slv)
• Assignments are still strongly typed, so lhs, rhs
  need to be same length, and this conversion must
  be done
• numeric_std overloads operators for use on types
  signed, unsigned, and their combinations with
  integers. SLV is NOT in the picture.
  Std_logic_vectors have no numeric representation
  at all even when you include the arithmetic
  libraries (numeric_std, or std_logic_arith). The
  only library that lets you treat slvs as numbers
  is std_logic_unsigned (or signed) which
  essentially just does the closely related type
  conversion for you.
• conversion between integer,signed,unsigned is
  done with to_signed, to_unsigned, to_integer

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Lab4 SUPER Simple TB
gen_clk process begin clk lt '1'
wait for 10 ns clk lt '0' wait for 10 ns
end process gen_clk tb PROCESS
variable address unsigned(2 downto 0)
"000" variable opcode unsigned(3 downto 0)
"0000" BEGIN -- wait for
the rising edge of the clock to make it --
easier to interpret on the WAVE window
wait until rising_edge(clk) write_enable lt
'1' adr lt "000" databus lt x"12"
wait until rising_edge(clk) adr lt "001"
databus lt x"01" wait until
rising_edge(clk) adr lt "010" databus lt
x"5a" wait until rising_edge(clk) adr lt
"011" databus lt x"00" -- a x0112,
bx005a wait until rising_edge(clk) adr lt
"100" databus lt x"03" --shift left by 3
wait until rising_edge(clk) adr lt "100"
databus lt x"80" -- add ab wait -- wait
forever END PROCESS -- End Test Bench
- User Defined Section
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State Machines

• Finite State Machines (FSM) are a key tool of
  logic design
• A synthesizer can perform state optimization on
  FSMs to minimize the circuit area / delay
• This optimization is only available if the FSM
  model fits templates

State Diagram for Pulse Generator
Timing Diagram for Pulse Generator
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State Machine Example
entity pulseGen is generic ( clkEdge
std_logic '1' edge
std_logic '1') port ( clk, resetn, sig
in std_logic result out std_logic
) end entity pulseGen architecture
state_machine of pulseGen is type states is
(start, waitForSig, found) signal
current_state, next_state states begin
state_logic process(current_state, sig) is
begin case current_state is when
start gt result lt '0'
if sig (not edge) then
next_state lt waitForSig else
next_state lt start end if
when waitForSig gt result lt
'0' if sig (not edge) then
next_state lt waitForSig else
--we have had a transition
next_state lt found end if
when found gt next_state lt start
result lt '0 when others gt
next_state lt start end case
end process state_register process(clk,
resetn) begin if resetn '0' then
current_state lt start elsif clk'event
and clk clkEdge then current_state lt
next_state end if end process end
architecture state_machine
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Implementation of Pulsegen
FPGA Implementation of Pulse Generator
what is state encoding?
State Diagram for Pulse Generator
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Worked Example Statemachines

• Use traffic light example
• Consider two templates

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State Encoding
type traffic_states is (red, yellow, green,
fl_yellow, f_red, turn_arrow ) signal
current_state, next_state traffic_states
Sequential encodes the states as a binary
number (frequently in order of long paths)
000,001,010,011,100,101
Only one flip-flop is active, or hot, at any one
time.
100000, 010000, 001000, 000100, 000010, 000001
One-Hot - The "One-Hot" encoding option will
ensure that an individual state register is
dedicated to one state. Only one flip-flop is
active, or hot, at any one time. One-hot encoding
is very appropriate with most FPGA targets where
a large number of flip-flops are available. It is
also a good alternative when trying to optimize
speed or to reduce power dissipation. Compact -
The "Compact" encoding option will minimizing the
number of state variables and flip-flops. This
technique is based on hypercube immersion.
Compact encoding is appropriate when trying to
optimize area..
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State Encoding
Gray - The "Gray" encoding option will guarantee
that only one state variable switches between two
consecutive states. It is appropriate for
controllers exhibiting long paths without
branching. In addition, this coding technique
minimizes hazards and glitches. Very good results
can be obtained when implementing the state
register with T or JK flip-flops. State reg might
go 000,001,011,010,110,111
specify encoding style to synthesis tool
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State Encoding
Why might state encoding make a difference? Speed
combinatorial decode of the state variable to
determine outputs and next state can
be made simpler via. one-hot for instance. State
transitions if combinatorial decode of output
is desired to have no glitches, the
encoding makes a difference. Size how many
FFs are required to represent all your states?

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Illegal States
given our states (red,yellow,green,fyellow,fred,
turn_arrow)
000
001
010
011
100
101
if they are encoded as above, we have 2 illegal
states. What will logic do when those states
are encountered?
case current_state is when red gt next_State
lt turn_arrow when turn_arrow gt next_state
lt green when green gt next_state lt
yellow. etc.
We dont really know..
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Dealing with State Machine

• Faulty Reset Circuitry (or none) could have you
  power-up in an illegal state
• Single-Event-Upsets in radiation environments can
  cause a flop to toggle, leaving your state
  machine in an illegal state
• Synchronization Errors on inputs
• setup/hold violation
• metastability

Consequences of illegal state entering is
unknown, but frequently result is wedged
machine, which doesnt recover
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Example Machine
SIMPLIFIED Flash Memory reading interface
idea of this is so that external environment can
read flash by simply putting an adr on the line,
and pulling readrq high. The state machine must
go off, and send commands to the flash to get
that piece of data, and the datardy signal will
go high when the data is rdy on the flash pins.
entity flashif is port ( clk in
std_logic -- assume 50 MHz reset
in std_logic -- active low address
in std_logic_vector(22 downto 0) readrq
in std_logic datardy out
std_logic --- signals to flash
iobus out std_logic_vector(7 downto 0)
ale out std_logic cle
out std_logic we out std_logic
re out std_logic ready_busy_b
in std_logic )
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State Diagram
type state_type is (waiting, -- waits for
readrq readcmd_latch_start, -- steps through
these states once per clock readcmd_latch_wait, re
adcmd_latch_wehigh, -- writes a read
command readcmd_latch_clelow, -- disables the
command latch adr0_latch_start, -- now tells the
flash the address adr0_latch_wait, adr0_latch_wehi
gh, adr9_latch_start, adr9_latch_wait, adr9_latch_
wehigh, adr17_latch_start, adr17_latch_wait, adr17
_latch_wehigh, adr_latch_deassert, waitfor_busy,
-- stays here till flash busy waitfor_notbusy, -
- stays here till flash not busy read_relow, --
tells flash to drive databus read_wait, -- waits
for slow access time read_rehigh -- this
state makes data re go high )
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Next_State Decoding
statelogic process (current_state,seq_access,rea
drq,sync_busy) begin case current_state is
when waiting gt if readrq '1'
then if seq_access '1' then
next_state lt read_relow
else next_state lt
readcmd_latch_start end if
else next_state lt
waiting end if when
readcmd_latch_start gt next_state lt
readcmd_latch_wait when
readcmd_latch_wait gt next_state lt
readcmd_latch_wehigh when
readcmd_latch_wehigh gt next_state lt
readcmd_latch_clelow when
readcmd_latch_clelow gt etc
Purely combinational process, only 1
output next_state
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Decoding States for output signals
datardy lt '1' when (current_state read_rehigh)
else '0' -- decode states for re signal
re_reg process(clk,reset) begin if (reset
'0') then re_int lt '1' elsif (clk '1' and
clk'event) then re_int lt next_re end
if end process re_reg re_logic
process(current_state,re_int) begin case
(current_state) is when read_relow gt
next_re lt '0' when read_rehigh
gt next_re lt '1' when others gt next_re
lt re_int end case end process re_logic
Output signals look at current_state to
determine their values. If signal is to be
treated as a clock by outside device, register
it (like re here)
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Onehot Encoding
DFFs
High Energy particle may disrupt the state of a
FF leaving us in an illegal state.
readrq
Comb Logic
waiting
readcmd_latch_start
readcmd_latch_wait
readcmd_latch_wehigh

If timing of readrq is such that it is right
before the clock, if delay paths are not matched,
then we could enter illegal state (wait ff could
say Im zero but readcmd.. may not update to
1 Now we are wedged with current state all
zeros.
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Reset Circuitry
statemach process(clk,reset) begin if
(reset '0') then current_state lt
waiting elsif (clk '1' and clk'event)
then current_state lt next_state end
if end process statemach
Without this, state machine may power up in
illegal state (in onehot it almost certainly
will.. since all 0s and and 1s are not valid
states)
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Dealing with illegal states
These problems are not specific to Onehot
encoding. They are simply magnified with the
scheme, since there are far more illegal states!

• Have a reset state obviously
• carefully synchronize all inputs
• If design is in an inaccessible place and can not
  be rebooted..etc. Make a safe state machine

use two dff for metastability issues
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Safe state machines
Others clause is typically not implemented by
the FSM extractor.. (there are no others, since
every one in the ennumerrated type is covered)
The synthesizer may call this the result of
reachability analysis. So it may be up to you
to generate reset logic which will reset the
machine and place it in a known state.
i.e. sync_reset_machine lt 0 when (state a)
or (stateb) else 1 Some synthesis tools
provide attributes for encoding machines that
include safe,onehot safe,grey etc.
This is hit-or-miss though, when REALLY
important. --gt
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State Machine Example (2)
architecture state_machine of pulseGen is
signal current_state, next_state
std_logic_vector(1 downto 0) constant
start std_logic_vector(current_state'range)
"00" constant waitForSig
std_logic_vector(current_state'range) "01"
constant found std_logic_vector(current_
state'range) "10" constant error
std_logic_vector(current_state'range)
"11" begin state_logic process(current_state,
sig) is begin case current_state is
when start gt result lt '0'
if sig (not edge) then
next_state lt waitForSig else
next_state lt start end if
when waitForSig gt result lt
'0' if sig (not edge) then
next_state lt waitForSig else
--we have had a transition
next_state lt found end if
when found gt result lt '1'
if sig (not edge) then
next_state lt waitForSig else
next_state lt start end if
when error gt result lt '0'
next_state lt start when
others gt next_state lt start
end case end process state_register
process(clk, resetn, next_state) begin
if resetn '0' then current_state lt
start elsif clk'event and clk clkEdge
then current_state lt next_state
end if end process end architecture
state_machine

• Notice the alternative way to define the states,
  as std_logic_vectors.
• There are certain circumstances, such as when a
  circuit will be exposed to a harsh environment,
  when it may not be desirable to allow the
  synthesizer to optimize the state machine
• This optimization may create a state-machine
  where if a single bit of a state register were to
  change, the state machine could enter an invalid
  state and not return.
• By explicitly defining all the states, we remove
  this possibility.
• In general this is NOT need it is recommended
  that enumerated types be used to define states.
• TURN FSM Extraction OFF

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Exam Materialall material covered in class,
homeworks, and assigned book chapters is fair ,
however here are some particulars

• you should be able to quickly construct basic
  design elements in synthesizable vhdl.
• e.g. make a d-flipflop w/ enable
• state machines
• simulation vs. synthesis
• mechanics of a process
• given simple design constraints, make
  synthesizable entity/architecture pair