Arithmetic Building Blocks

1
Arithmetic Building Blocks
2
A Generic Digital Processor
3
Building Blocks for Digital Architectures
Arithmetic unit

Bit-sliced datapath
adder
-
(
, multiplier,
shifter, comparator, etc.)
Memory
- RAM, ROM, Buffers, Shift registers
Control
- Finite state machine (PLA, random logic.)
- Counters
Interconnect
- Switches
- Arbiters
- Bus
4
Bit-Sliced Design
5
Full-Adder
6
The Binary Adder
7
Express Sum and Carry as a function of P, G, D
8
The Ripple-Carry Adder
9
Complimentary Static CMOS Full Adder
10
Inversion Property
11
Minimize Critical Path by Reducing Inverting
Stages
12
The better structure the Mirror Adder
13
The Mirror Adder

• The NMOS and PMOS chains are completely
  symmetrical. This guarantees identical rising and
  falling transitions if the NMOS and PMOS devices
  are properly sized. A maximum of two series
  transistors can be observed in the
  carry-generation circuitry.
• When laying out the cell, the most critical issue
  is the minimization of the capacitance at node
  Co. The reduction of the diffusion capacitances
  is particularly important.
• The capacitance at node Co is composed of four
  diffusion capacitances, two internal gate
  capacitances, and six gate capacitances in the
  connecting adder cell .
• The transistors connected to Ci are placed
  closest to the output.
• Only the transistors in the carry stage have to
  be optimized for optimal speed. All transistors
  in the sum stage can be minimal size.

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Quasi-Clocked Adder
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NMOS-Only Pass Transistor Logic
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NP-CMOS Adder
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NP-CMOS Adder
C
o1
S
1
A
1
B
1
S
0
A
0
B
0
C
i0
18
Manchester Carry Chain
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Sizing Manchester Carry Chain
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Carry-Bypass Adder
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Manchester-Carry Implementation
22
Carry-Bypass Adder (cont.)
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Carry Ripple versus Carry Bypass
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Carry-Select Adder
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Carry Select Adder Critical Path
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Linear Carry Select
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Square Root Carry Select
28
Adder Delays - Comparison
29
LookAhead - Basic Idea
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Look-Ahead Topology
31
Logarithmic Look-Ahead Adder
32
Brent-Kung Adder
33
The Binary Multiplication
34
The Binary Multiplication
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The Array Multiplier
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The MxN Array Multiplier Critical Path
Critical Path 1 2
37
Carry-Save Multiplier
38
Adder Cells in Array Multiplier
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Multiplier Floorplan
40
Wallace-Tree Multiplier
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Multipliers Summary
42
Design as a Trade-Off
43
Layout Strategies for Bit-Sliced Datapaths
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Layout of Bit-sliced Datapaths
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Layout of Bit-sliced Datapaths