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DCD company and products presentation

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100% software compatibility with industry standard 80C51. Risk free silicon proven IP's ... Tests with reference responses. Technical documentation ... – PowerPoint PPT presentation

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Title: DCD company and products presentation


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OVERVIEW
  • 100 software compatibility with industry
    standard 80C51
  • Risk free silicon proven IP's
  • Fastest 8051 architecture on the market
  • Speed 80C51 14.75
  • Special care of the Power Consumption
  • Advanced Power Management Unit
  • Two selectable configurations
  • Harvard
  • von Neumann
  • Mixed
  • Built in Hardware on chip debugger DoCDTM
  • An industry-leading combination of high
    performance, low power, and small die size
  • Easy system integration - to peripherals,
    coprocessors, and memories
  • Easy customization for adaptability to a wide
    range of applications
  • A choice of robust third party development and
    software tools
  • An ASIC-style implementation methodology
  • Technology independent

Page 2
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CPU FEATURES
  • Software compatibility with industry standard
    80C51
  • Dhrystone 2.1 benchmark program runs from 11,45
    to 14,73 times faster than the original 80C51 at
    the same frequency
  • 24 times faster multiplication and 12 times
    faster addition
  • Up to 13,868 VAX MIPS at 100 MHz
  • User programmable Program and External Data
    Memory Wait States
  • De-multiplexed Address/Data bus to allow easy
    connection to memory
  • Dedicated signal for Program Memory writes.
  • Interface for additional Special Function
    Registers
  • Fully synthesizable, static synchronous design
    with no internal tri-states
  • Scan test ready
  • 2.0 GHz virtual clock frequency in a 0.25u
    technological process

Page 3
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PERIPHERALS
  • Wide range of available peripherals
  • DUSB2 USB 2.0 device including
  • HID Human Interface Device
  • MS Mass Storage
  • Audio devices
  • Parallel I/O Ports
  • UARTs
  • Timers / Counters with Compare Capture
  • Watchdog Timer
  • Power Management Unit
  • I2C bus interfaces Master and Slave
  • Serial Peripheral Interface SPI Master/Slave
  • Floating Point Math Coprocessors
  • Media Access Controller DMAC
  • 32-bit Multiply Divide Unit
  • Data pointers

Page 4
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CONFIGURABILITY
Easy core configuration using constants in IP
Core package
Page 5
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CONFIGURATIONS
Easy selection from few typical configurations
Page 6
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DELIVERABLES
  • Source code
  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • FPGA netlist
  • VHDL VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • NCSim automatic simulation macros
  • Tests with reference responses
  • Technical documentation
  • Installation notes, Instructions set details
  • HDL core specification
  • Datasheet
  • Synthesis scripts
  • Example application

VHDL Verilog
Page 7
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IMPROVEMENTS
The most commonly used arithmetic functions and
their improvements are shown in table below.
Improvements were computed as 80C51 clock
periods divided by DP8051 clock periods
required to execute identical functions. More
details are available in core documentation.
Page 8
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PERFORMANCE
Dhrystone Benchmark Version 2.1 was used to
measure Core performance. Dhrystone 2.1 benchmark
program runs from 11,45 to 14,73 times faster
than the original 80C51 at the same frequency.
Page 9
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BENEFITS
Same performance lower power
consumption Same clock frequency higher
performance
Page 10
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PERFORMANCE
Extremely high performance up to 300 MHz in
Hynix 0.18 library, equivalent performance to
original 80C51 clocked with 4296
MHz. 358 times higher performance
(80C51 running at 12 MHz)
Page 11
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ON-CHIP DEBUGGING
DoCDTM DCD on-chip Debugging System is a useful
tool, dedicated to DCD's 8051/80390 IP Cores.
System consists of three major parts
DoCD Debug Software Windows debugging application
Hardware Assisted Debugger HAD2 A small
hardware adapter
Hardware Debug IP Core Integrated on-chip with
processor core in silicon
Page 12
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DoCD Overview
  • Real-time debugging
  • Non intrusive
  • Supports all DCDs 8051 and 80390 IP Cores
    families
  • Two mode of operation
  • hardware debugger
  • software simulator
  • Supports all major high level C/ ASM tools
  • Extended OMF-51 produced by Keil compiler
  • OMF-51 produced by Tasking compiler
  • OMF-51 produced by Franklin compiler
  • Standard OMF-51 produced by some 8051 compilers
  • Extended OMF-251 produced by Keil compiler
  • NOI format file produced by SDCC-51 compiler
  • Intel HEX-51 format produced by each 8051
    compiler
  • Intel HEX-386 format produced by each 80390
    compiler
  • BIN format produced by each 8051 80390
    compiler

DoCD evaluation board
Page 13
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DoCD IP Core
  • Processor execution control
  • Run, Halt
  • Reset, hot-attach
  • Step into instruction
  • Skip Instruction
  • Read-write all processor contents
  • Unlimited number of OPCODE real-time
    breakpoints
  • Hardware execution breakpoints
  • Program Memory
  • Internal (direct) Data Memory
  • Special Function Registers (SFRs)
  • External Data Memory
  • Hardware breakpoints activated at a
  • certain program address (PC)
  • certain address by any write into memory
  • certain address by any read from memory
  • certain address by write a required data
  • certain address by read a required data
  • Automatic adjustment of debug data transfer
  • Communication interface
  • TTAG interface v4.70 and above
  • JTAG interface v4.00 and above
  • DTAG three wire communication v3.xx
  • Fully static synchronous design
  • No internal tri-states

Page 14
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DoCD SOFTWARE
  • Three working modes
  • Source Level Debugging
  • C level hardware/software breakpoints
  • C code execution
  • ASM code execution
  • ASM, C source view of code
  • Symbol Explorer provides hierarchical tree
    view of all symbols
  • Contents sensitive Watch window
  • Symbolic debug
  • Unlimited number of OPCODE real-time breakpoints
  • Real-time hardware breakpoints
  • 1024 steps deep Software Trace
  • Load Program Memory content from
  • OMF-51, extended OMF-51 files
  • OMF-251 file
  • Intel HEX-51, HEX-386 files
  • BIN file
  • Auto refresh of all windows
  • Dedicated windows for peripherals
  • Configurable auto refresh time period
  • Status bar containing real processor
  • speed
  • The system runs on a Windows
  • Supports software tools from
  • Keil, IAR, Archimedes, Tasking, Franklin,
    SDCC

Page 15
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DoCD HAD Hardware Assisted Debugger
  • USB communication interface to target host at
    FULL speed
  • Synchronous communication interface to Debug IP
    Core
  • TTAG interface Debug IP v4.70 and above
  • JTAG interface Debug IP v4.00 and above
  • DTAG interface Debug IP v3.xx
  • Supports four I/O voltage standards
  • 3.3 Volt systems
  • 2.5 Volt systems
  • 1.8 Volt systems
  • 1.5 Volt systems
  • Single power supply directly from USB
  • Small physical dimensions pendrive style
    package

Page 16
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