APDs and Electronics System Design

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APDs and Electronics System Design

• Roger Rusack
• Minnesota

2
Outline

• Review of what we said in the proposal.
• Proposal from Hamamatsu
• What is between us and construction.

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APD Housing Concepts

• We are making 30,000 modules so the design has
  to begin with manufacturability.
• We need to align the APDs with the fibers - the
  better we do this the larger the fiber or the
  smaller the APD.
• The square pixel structure is not optimized for
  the two-fiber readout.
• We should stay within the same surface area of
  silicon to keep close to the same price.

4
Current thinking

• We will use an APD array mounted on a PCB using
  flip-chip technology. This provides an
  alignment of 10??m to the PCB. Alignment is
  reduced to aligning the fibers to the PCB.
• Cooling by thermo-electric coolers to -15oC.
• Readout through very front-end designed by Tom
  Zimmerman.
• Front-end readout architecture still under
  discussion.

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Proposed APD Layout
Solder Bumps
Apperture in PCB for fibers.
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APD pixels
Hole for Fiber connector
PCB substrate
2.3 mm gap
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Basic Module concept.
Thermally Conductive Mousse
Present in one option
Support Ring
APD
ASIC
ADC
FPGA
TE Cooler
PCB
FiberConnector
FPGA for signal processing, IO and slow control.
Thermally isolated volume.
Air Gap
APD, ASICs and FPGA mounted onto PCB. Casing made
of injection molded components used to align
fiber connector and insulate/isolate APD.
Other options are being considered see talk by
Stuart Mufson
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Status.

• Tests at Hamamatsu
• Flip chip method tested and Hamamatsu is happy
  with the result - We have not seen the detailed
  results.
• Minimum distance to border is understood.
• APD layout with 10 pF matched to fibers defined.
• Quote from Hamamatsu
• NRE for wafer design and TE cooler attachment and
  
• 20 prototypes in aro. 6 months 10,000 ea.
• 40 prototypes in same time scale 6,250 ea.

Important point is that schedule is only 6 months.
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Front-End Readout options.

• Two options have been considered for the design
  of the front-end readout the APD.
• Harvard design see talk by John Oliver later.
• Tom Zimmerman has designed a version of the
  front-end ASIC.

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Basic Concept

• Optimize design for low-noise readout during the
  spill.
• 32-channels to match the number of channels in a
  module.
• Track and hold amplifier which is sampled every
  500 nsec for 30 microseconds to cover spill.
  Samples are stored in a 64 deep switched
  capacitor array (64 32).
• After spill begin conversion process.
• 32 channels compared with linear ramp. 10-bit
  resolution.
• Covert next ramp and send out data.
• Repeat until all channels digitized.
• Digitize difference between odd neighbor cells OR
  digitize each cell and subtract digitally.

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Main Operation Spill Mode
Read Amplifier
Charge sensitive pre-amp
Shift Register
64 deep capacitor array
Latch
Comparitor
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32 input channels
10
Linear Ramp Generator
Readout strobe
Collect signal in SCA
Digitize Later
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Alternative Operation Fast Digitization Mode.

• Variants on the standard operation are included
  in the design.
• Direct in to latch.
• Non-linear ramp.
• Complete digitization in 400 nsec.

Read Amplifier
Latch
Comparitor
Non-linear ramp
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Status

• Design complete.
• Full simulations complete. Calculated noise level
  with 10 pf and 250 nsec shaping is 150 electrons.
  Reality hope for expect 200.
• Next step layout and produce short run in 0.25 m
  process.
• Plan is to submit this with other readout options.

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Alternative Readout

• Alternative readout architecture which has same
  operation in both spill and supernova detection
  modes.

See talk by John Oliver later.
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Development Schedule

• To go from initial design concepts to launch
  production of 30,000 APD modules we need to
• Design front-end readout ASIC.
• Design front-end board with all ancillary
  circuits.
• Prototype and test APD modules.
• Design, make and qualify cooling system.
• Build automated module testers for production.
• We need final versions of the prototype in
  quantities of 10,000 channels by Feb 2007.
• We need to start production of modules by Oct
  2008.
• Installation May 2009.

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Immediate Tasks

• APD TE cooler design - Hamamatsu 6 Months
• Front-end electronics
• ASIC design, layout and fabrication - FNAL
  Harvard.
• PCB design layout and fabrication - FNAL.
• 400 V bias supply - Cockroft Walton or
  distributed line?
• TE cooler and controller.
• Test modules.
• Revisions.
• Module tester.

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Short Term Schedule
ASIC development
DesignRevision
Test with prototype
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Long Term Schedule
Test with prototype
Start mass productionJan/09
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Other Major Issues

• Cooling TE cooler with water or air?
• Beam signal and clock distribution.
• Low Voltage network - Could be extensive.
• Trigger and DAQ
• Need to have an agreed set of specifications.

To be addressed in the coming months.
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Summary

• APD structure
• Some progress with APD design. Optimized for 32
  channel modularity.
• ASIC design of one version complete. Designed to
  meet beam and SN detector requirements.
• Schedule
• There is much to be done on a short timescale.