Circuit Synthesis under Uncertainty using DesignTime Optimization and PostFabrication

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Circuit Synthesis under Uncertainty using
Design-Time Optimization and Post-Fabrication
M. Mani, C. Caramanis, and M. Orshansky University
of Texas at Austin
Target Applications Adjustable Power-Efficient
Buffers on Timing-Critical Paths
Adjustable Affine Optimization
Parametric Yield Loss and Mitigation by
Post-silicon Tuning

• Process variability results in parametric yield
  loss
• Exponential dependence of leakage on process
  spread
• Inverse correlation between leakage and
  performance
• Tuning chips after manufacturing is an effective
  yield enhancing strategy
• Adaptive body biasing (ABB) tightens Fmax spread
• Improves power limited parametric yield

• Target application power-efficient tapered
  buffers in timing-critical paths
• E.g. embedded SRAM Both timing paths and power
  are dominated by buffer chains driving large
  wordline capacitances
• Need to guarantee correct memory access time in
  the presence of process variations
• Use an adaptive strategy to reduce average energy
  consumption in large buffers
• Pre-design redundant implementations and select
  after manufacture depending on uncertainty
• Design tuning based on
• Buffer stages with different drive strength
• Buffer stages using different threshold voltage
• Can be implemented using a tri-state buffer
  configuration
• Adjust drive strength by selecting a branch

• Adjustable optimization
• Some variables (second-stage) are allowed to
  depend on realizations of uncertain parameters
• Output of adjustable optimization is set of
  first-stage decisions and a policy
• Policy prescribes how to react to future
  realizations of uncertain variables
• General adjustable problems with arbitrary
  dependence of variables on uncertain parameters
  are NP-hard
• Adjustable variables are constrained to be affine
  functions of the uncertain variables
• Can use fast interior point methods

Adaptable Buffer Design Formulating the Problem
Adaptable Buffer Design Solving the Problem
Measurement Complexity

• Consider only variability in channel length L
• Two possible partitions with lo the truncation
  point
• Two different buffer configurations
• Select buffer 1 with probability a1 buffer 2 with
  probability a2
• Can re-write the problem as
• where FL1, FL2 cdf of variables
• For each truncation point, we solve a geometric
  program
• Find optimal truncation point by a linear sweep
• This describes the optimal policy
• Similar strategy for handling variability in both
  L andVth
• Seeks partitioning of 2-D uncertainty set

• A two-stage problem under uncertainty but with
  finite adaptability
• First stage size buffers
• Second stage determine policy for selecting a
  branch
• Minimize average power with satisfactory
  timing-yield
• Strategy solving above is equivalent to finding
  a partition of uncertainty set
• ?i - partitions of uncertainty set, xi - first
  stage decision, yi - second stage decisions
• A second-stage decision yi corresponds to a
  partition ?i

• Measurement infrastructure is an essential part
  of tuning methodology
• Measurement complexity, k
• Represents the amount of known information about
  the structure of variability
• Use a single measure k kl kv
• Effectiveness of tuning depends on measurement
  complexity
• Determines selection of optimal policy

Benchmark Results
Formulating Separable Objective Function
Problem Formulation and Solution Strategy

• Use first order delay and log-leakage models
• Leakage is log-normal. Expected value
• Using affine policy expression
• f0, f1, and f2 are linear functions of p0, p1
  and p2
• We separate dependence on w and p
• Io b w, where b is leakage per unit device
  width
• Let
• For a vector of gate widths w, expected block
  leakage

• Minimize expected leakage power under timing
  yield
• Objective function is linear in size w and
  exponential in p
• Delay constraints are second order conic path
  delays
• Final optimization problem
• For efficient solution, solve as a two phase
  optimization
• w phase sizing at fixed body bias
• Second Order Conic Program
• p phase find body bias at fixed size
• Non-linear, linearize around a fixed point

where

• Leakage power reduction on average is 21
  compared to design time only optimization

Co-Optimization vs. Heuristic Post-Sizing Tuning
Delay Spread Reduction
Conclusions

• Joint optimization should also be superior to
  disjoint tuning steps
• Performed comparison against heuristics that
  performs post silicon tuning separately after
  sizing
• Difficult to pick optimal value of body bias for
  cells in design
• Performs worse than joint optimization
• Delay spread is higher
• Leakage power consumption is greater

• Joint co-optimization enables synergy between
  design time and post silicon steps
• Developed foundation for joint design-time and
  post-silicon optimization
• Up to 20 savings in leakage power can be
  obtained
• Introduction of metrics that enable designers to
  assess the complexity of biasing circuitry
  needed
• Computationally efficient formulation using
  adjustable robust optimization
• Good run-time behavior

• Joint optimization is successful in tightening
  the delay distribution