State Machines

1
State Machines

• Anselmo Lastra

2
Administrative

• Hows the pace of the course?

3
Topics

• How to design machines that go through a sequence
  of events
• Basically close this loop

4
Lab Preview

• Digital lock
• Youll need clock
• Will provide code for slowing clock
• Next

5
Counter

• module cntr32(clk, res, out)
• input clk
• input res
• output out
• reg 310 count
• always _at_ (posedge res or posedge clk)
• if(res)
• count lt 0
• else
• count lt count 1
• assign out count22 // Could use parameter
• endmodule

What does this do?
6
Button and Debouncing

• Button normally high
• Mechanical switches bounce
• Go H and L a number of times
• Well want to
• debounce
• synchronize

7
Flip-Flop for pushbutton

• module button_test(clk, btn, q)
• input clk
• input btn
• output q
• reg q
• always _at_ (posedge clk)
• begin
• if(btn 1)
• q lt 1
• else
• q lt 0
• end
• endmodule

What is this?
8
Simple Module for an Example

• module led_on(clk, button, s6)
• input clk
• input button
• output s6
• wire clkb
• cntr32 C1(clk, 0, clkb)
• button_test B1(clkb, button, s6)
• endmodule

• clk to board clock, P88
• button to pushbutton, P93
• Why button?
• s6 to one of LED segments

9
Things to Think About

• Can I press button and not light LED?
• What happens if I hold button down for a long
  time?
• What effect will changing period of clkb have?
• On LED
• On button debouncing

10
Analysis of Sequential Circuits

• Earlier we learned how to analyze combinational
  circuits
• Now extend to synchronous sequential
• Include time
• Well use state tables and state diagrams

11
Input Equations

• Can describe inputs to FF with logic equations

12
Another Example
13
Time is Implied

• Note that last circuit used the
• Previous state to determine next state
• State and inputs to determine output
• Synchronous circuit
• When are transitions?
• So timing is discrete

14
State Table

• Just truth table with state added

15
Two Dimensional Table

• Same thing, different layout

16
Sequential Circuit Types

• Moore model outputs depend on states

• Mealy model outputs also depend on inputs

17
State Diagram

• Alternative representation for state table
• Moore-gt

Inputs
State/Output
18
Mealy Model

• Output depends on input and state

Input/Output
19
State Table vs. Diagram

• Same information
• Table is perhaps easier to fill in from
  description
• Diagram is easier for understanding and writing
  code
• You can label states with English description
• Eliminate repetitive portions (for example, when
  reset is an input)

20
One Shot

• Help me analyze this one
• What does it do?

21
Design Procedure

• Take problem description and refine it into a
  state table or diagram
• Assign codes to the states
• Write Verilog
• See example in a moment
• Designing with gates and FFs more involved
  because you have to derive input and output
  functions

22
Example Sequence Recognizer

• Circuit has input, X, and output, Z
• Recognizes sequence 1101 on X
• Specifically, if X has been 110 and next bit is
  1, make Z high

23
How to Design States

• States remember past history
• Clearly must remember weve seen 110 when next 1
  comes along
• Tell me one necessary state

24
Beginning State

• Some state, A
• If 1 appears, move to next state B

Input / Output
25
Second 1

• New state, C
• To reach C, must have seen 11

26
Next a 0

• If 110 has been received, go to D
• Next 1 will generate a 1 on output Z

27
What else?

• What happens to arrow on right?
• Must go to some state.
• Where?

28
What Sequence?

• Here we have to interpret problem
• Weve just seen 01
• Is this beginning of new 1101?
• Or do we need to start over w/ another 1?
• They decide that its beginning (01)

29
Cover every possibility

• Well, must have every possibility out of every
  state
• In this case, just two X 0 or 1
• You fill in other cases on board
• Lift screen
• Next slide

30
Fill in
31
Answer From Book
32
State Minimization

• When we make state diagram, do we need all those
  states?
• Some may be redundant
• State minimization procedures can be used
• We wont cover

33
State Table

• Just fill in from diagram if need it
• I find diagram more useful

34
How to code in Verilog

• Instead of learning how to hand design (Sections
  4-6 and 4-7)
• Learn how to code this in Verilog

35
Verilog Case Statement

• Similar to sequence of if/then/else
• case (expression)
• case statements
• other case statements
• default statements // optional
• endcase
• Example in a moment

36
Parameter Just Shorthand

• module seq_rec_v(CLK, RESET, X, Z)
• input CLK, RESET, X
• output Z
• reg 10 state, next_state
• parameter A 2'b00, B 2'b01,
• C 2 'b10, D 2'b11

Notice that weve assigned codes to the states
more later
37
Next State

• always _at_(X or state)
• begin
• case (state)
• A if (X 1)
• next_state lt B
• else
• next_state lt A
• B if(X) next_state lt Celse next_state lt
  A
• C if(X) next_state lt Celse next_state lt
  D
• D if(X) next_state lt Belse next_state lt
  A
• endcase
• end

The last 3 cases do same thing. Just sparse
syntax.
38
On Reset or CLK

• always _at_(posedge CLK or posedge RESET)
• begin
• if (RESET 1)
• state lt A
• else
• state lt next_state
• end

Notice that state only gets updated on posedge of
clock (or on reset)
39
Output

• always _at_(X or state)
• begin
• case(state)
• A Z lt 0
• B Z lt 0
• C Z lt 0
• D Z lt X ? 1 0
• endcase
• end

40
Demo

• Lets try the book code on an example

41
Comment on Book Code

• Could shorten
• Dont need next_state, for example
• Can just set state on clock
• Dont need three always clauses
• Although its easier to have combinational code
  to set output be separate

42
Synthesis

• Sometimes unexpected latches created
• always will try to synthesize FF
• if (select) out lt A
• To save old value if select ! 1
• If cover all possibilities, no FF
• if (select) out lt A
• else out lt B

43
Today

• Make simple state machines
• Code them in Verilog
• Next Time
• Test review
• Info for next lab