16 bit complex multiplier

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16 bit complex multiplier

• Project Design FDR DEC 12th 2005
• Team Leader Elie Dagher
• Course ECE 715
• Partners Tri Le

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Table of Content

• Project definition--------------------------------
  ------------------ 3
• Goals -------------------------------------------
  ------------------- 4
• Project specifications----------------------------
  ----------------- 5
• Strategy------------------------------------------
  ------------------- 6
• Design Order -------------------------------------
  -----------------7
• Half adder ---------------------------------------
  ------------------ 8-10
• Full adder ---------------------------------------
  ------------------- 11-14
• Multiplier ---------------------------------------
  ------------------- 15-20
• 8 bits Adder -------------------------------------
  ------------------ 21-26
• 8 bits subtractor --------------------------------
  ------------------- 28-30
• Full design w/o FFs ------------------------------
  ---------------- 31-36
• Full design w/ FFs -------------------------------
  ----------------- 37-42
• Full Design Layout -------------------------------
  ---------------- 43
• Pin Assignment -----------------------------------
  ---------------- 44

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Project Definition

• Project description The goal of this project is
  to design a CMOS 16 bit complex multiplier which
  can used as part of an ASIC version of a
  fingerprint authenticator.
• The purpose of this project is to develop
  a library of component for a 16-point, radix_4
  Fast Fourier Transform algorithm.

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Projects Goal

• Design a 16 bits Complex Multiplier CMOS hchip.
• The chip should be able to compute the
  multiplication of 2 complex numbers (ajb)(cjd)
• Expand (ajb)(cjd) (ac-bd)j(adbc)
• a,b,c,d are 4 bits each.
• So we need to design the 3 main arithmetic
  operators
• -4X4 Multiplier
• -8 bits Adder
• -8 bits Subtractor

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Project Specifications

• Suggested clock speed 100 MHz (If the speed of
  100 MHz can not be achieved in AMI05 technology
  then a lower frequency is acceptable)
• Algorithm radix-4
• Arithmetic 16 bit fixed point, 2s complement
• Complex arithmetic operations should be divided
  into smaller tasks (pipelining) if the assumed
  target frequency could not be achieved otherwise
• All control and status signals should follow the
  same standard
• All components should have a clock input (CLK),
  reset (RST)
• Arithmetic operators should contain a status line
  (OVFL) indicating whether an overflow has
  occurred

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Strategy

• Understand the goal of the project, and design it
  on scratch.
• Do some research about the components that are
  going to be used.
• Design the project using Design Architecture.
• Simulate the design using Eldo.
• Create an Automated Layout of the design using
  the IC station.
• Add PadFrames using Design Architect-IC.
• Use MACH-TA for Simulating Digital Circuits.
• Send the final design to MOSIS for fabrication.

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Design Order

• -Half Adder (needed to design the multiplier)
• -Full Adder (needed to design the 16 bits
  multiplier, the 8 bits adder, and the 8 bits
  subtractor)
• -4X4 bit Multipliers
• -8X8 bit Adder
• -8X8 bit Subtractor
• -Final design with no Latches (Asynchronous)
• -Block of 8 bit Latches (needed to make the
  digital circuit synchronous)
• -Final design with Latches (Synchronous)

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Half Adder design

• Half Adder (HA) Adds two inputs A and B. The
  result is 0 , or 1 and a carry out.

Fig.1-a Truth Table for HA
Fig.1-b Block representation for HA
Half Adder outputs equations Cout (carry out)
AB S (sum) A XOR B
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Half Adder Design (cont.)

• Half Adder with 2 inputs A, and B and 2 outputs
  Cout and Sum.
• (Note XNOR gate followed by an
  Inverter were used instead of a XOR gate,
• because there was a problem
  with the XOR gate in Design Architect.)

Cout (carry out) AB S (sum) A XOR B
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Half Adder Design (cont.)Timing Diagram
Tdelay150 Ps
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Full Adder design

• Full Adder (FA) Add two inputs A and B. The
  result is 0 , 1 or 2 so two bits are required to
  represent the value.

Fig.2-a Truth Table for FA
Fig.2-b Block representation for FA
Full Adder outputs equations Cout (carry out)
BCin ACin AB S (sum) A XOR B XOR Cin
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Full Adder Design (cont.)

• Least number of components required to implement
  a 2 bits Full Adder with Carry In for minimum
  Delay.

Full Adder outputs equations Cout (carry out)
BCin ACin AB S (sum) A XOR B XOR Cin
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Full Adder Design (cont.)

• Full Adder with 3 inputs A, B, and Cin, and 2
  outputs Cout and Sum.
• (Note XNOR gate followed by an
  Inverter were used instead of a XOR gate,
• because there was a problem
  with the XOR gate in Design Architect.)

Fig.4-a Full Adder
Fig.4-b Block of a Full Adder
Cin AB BC AC Sum A () B () C
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Full Adder Design (cont.)Timing Diagram
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4x4 Bits multiplier

• 4X4 Multiplier Multiplies two 4 bits inputs
  each, and result in a 8 bits output.

Fig.5 4x4 array multiplier. The squared block is
Full Adder, and the other one is the Half Adder.
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4x4 Bits multiplier (cont.)

• Its made out of 12 Full Adders cascaded.
• To minimize the delay, 8 Full Adders and 4 Half
  Adders can be used.

Fig.6 Multiplication of 4X4 bits
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4x4 Bits multiplier (cont.)
Fig.7 Design of a 4X4 Multiplier
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4x4 Bits multiplier (cont.)

• The Multiplier takes two 4 bits numbers, and
  results in one 8 bits number.
• There are four of 4X4 multipliers are going to be
  used in the design.
• The Multipliers sign multipliers

Fig.8 Block of a 4X4 Multiplier
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4x4 Bits multiplier (cont.)Timing Diagram (4X4
bit input)
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4x4 Bits multiplier (cont.)Timing Diagram (8 bit
Output)
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8 Bits Adder

• Made out of two 4X4 Full Adders cascaded as show
  in the figure below. The Carry out of the first
  is connected to the carry in of the second. The
  last carry out is the Overflow bit.

Fig.9 An 8 bits Adder made out of two 4x4 bits
adders cascaded
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8 Bits Adder (cont.)

• 4x4 Bits Adder - Made out of four Full Adders
  cascaded as show in the figure below. The Carry
  out of the first is connected to the carry out of
  the second.

Fig.10 A 4x4 bits Adder made out 4 Full Adders
cascaded
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8 bits Adder (cont.)

• To get an 8 bits adder we can integrate two 4x4
  bits adders. This 8 bits adder takes two 8 bits
  numbers, with a carry in and returns one 8 bits
  number with a carry out.
• The last carry out bit is the Overflow bit.
• One Block of 8 bits adder is needed in the final
  design.

Fig.11 Block of an 8 bits adder
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8 bits Adder (cont.)Timing Diagram ( first 8
inputs)
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8 bits Adder (cont.)Timing Diagram ( second 8
inputs)
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8 bits Adder (cont.)Timing Diagram ( 8 bit
output)
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8 Bits Subtractor

• The 8 bits Subtractor is made out an 8 bits
  Adder, with the 8 bits of the second number
  complimented, and a high signal applied to the
  carry in bit.
• The last carry out is the Overflow bit
• The 8 bits subtractor takes two 8 bits numbers.
  It adds the 8 bits of the first number to the
  second compliment of the second number. It
  results in an 8 bits number, and one Overflow bit.

Fig.12 An 8 bits subtractor
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8 bits Subtractor (cont.)Timing Diagram( 1st 8
input)
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8 bits Subtractor (cont.)Timing Diagram( 2nd 8
input)
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8 bits Subtractor (cont.)Timing Diagram( 8 bit
output)
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Final Design (Asynchronous)without FlipFlops
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Final Design (Asynchronous) (cont.)Timing
Diagram ( First 8 inputs)
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Final Design (Asynchronous) (cont.)Timing
Diagram ( second 8 inputs)
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Final Design (Asynchronous) (cont.)Timing
Diagram (8 bits output Real)
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Final Design (Asynchronous) (cont.)Timing
Diagram (8 bits output Img.)
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Final Design (Asynchronous) (cont.)Timing
Diagram (Max Delay)
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Block of Latches Design

• We need the Flip Flops to synchronize the
  circuit.
• We need it at the input, and before the output to
  erase the glitches in the signals.

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Final Design (Synchronous)with Latches
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Final Design (Synchronous) (cont.)Timing
Diagram ( First 8 inputs)
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Final Design (Synchronous) (cont.)Timing
Diagram ( second 8 inputs)
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Final Design (Synchronous) (cont.)Timing
Diagram (8 bits output Real)
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Final Design (Synchronous) (cont.)Timing
Diagram (8 bits output Img.)
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Layout of the Final Design
Fig.
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Pin Assignment

• The maximum allowable number of pins for the
  chip is 40
• Pins. In our design we are going to have
• 16 pins for input
• 16 pins for output
• 1 pin for each VDD, GRND, RESET, Clock
• 2 overflow pins.
• It comes out to be 38 pins total.

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Whats next?

• Add PadFrames using Design Architect-IC.
• Use MACH-TA for Simulating Digital Circuits.
• Send the final design to MOSIS for fabrication.

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Task Assignment

• Elie did most of the design.
• Tri did the testing and simulations.
• We both did the final design and layout.

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References

• http//www.phys.ualberta.ca/gingrich/phys395/note
  s/node129.html
• http//www.mosis.com/
• http//www.ece.unh.edu/courses/ece715/links.htm
• http//www.ece.cmu.edu/lowpower/cicc98.pdf

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Comments

• It was a very helpful course to get a better
  understanding of VLSI chips. We learned a lot in
  this class and it was a nice experience.
• It will definitely look good on our resumes.

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Special Thanks

• Special Thanks to Prof. Andrzej Rucinski
• We would also to thank Francis C. Hludik
• And the TAs Thomas and Jakub. And the
  Classmates for their help.

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Any Questions?