Preparatory Design Studies MROD-X - PowerPoint PPT Presentation

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Preparatory Design Studies MROD-X

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... simulation (Smart-Models) of the setup - Okay! Real life test - Okay! ... Made LED On/Off via RS232 system, using PowerPC core Peripherals. Peter Jansweijer ... – PowerPoint PPT presentation

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Title: Preparatory Design Studies MROD-X


1
Preparatory Design StudiesMROD-X
  • Use Xilinx Virtex II Pro
  • RocketIO
  • PowerPC
  • Port the current MROD-In design from Altera to
    Xilinx

2
MROD-In design fromAltera to Xilinx
  • Altera
  • APEX20K200EQC240-1
  • Total logic elements
  • 5605 / 8320 (67 )
  • Total ESB bits
  • 15360 / 106496 (14 )
  • Total pins
  • 168 / 171 (98 )
  • Xilinx
  • XC2VP7FG456-7
  • Number of SLICEs
  • 2898 out of 4928 (58)
  • Number of RAMB16s
  • 3 out of 44 (6)
  • Number of External IOBs
  • 168 out of 248 (67)

Note 1 Rule of thumb 70 FULL. If you try to
put more in your FPGA then youll probably face
routing and timing problems! Note 2 1 Xilinx
SLICE ( 2 Logic Cells) 2 Altera Logic
Elements
3
Virtex-II Pro Development Board
4
Virtex-II Pro Evaluation Kit
5
GOL Test Board
6
SFP Evaluation Kit
7
GOL to RocketIO test
GOL Test Board
Development Board
Xilinx Virtex-II Pro FPGA
Start
Insert Error
Reset
Status LEDs
50 MHz
Event Data ROM
25 MHz
Altera FPGA
Idle
1 Gb/s
Run
Event Data ROM
Rocket IO
GOL
?
Okay
Fault
8
GOL to RocketIO test
9
GOL to RocketIO testResults
  • Xilinx ISE RocketIO placement problem -gt Solved
  • Back-annotated simulation (Smart-Models) of the
    setup -gt Okay!

Start
Start
Insert Error

Reset
  • Real life test -gt Okay!

10
To Be DoneTest FPGA to FPGA Data Links Plus
Flow Control
Evaluation Kit
Development Board
Xilinx Virtex-II Pro FPGA
Xilinx Virtex-II Pro FPGA
1.6 Gb/s (160 MB/s)
Full
Empty
Rocket IO
Rocket IO
FIFO
FIFO
Data
Data
11
PowerPC core Evaluation
  • Learn to use Xilinx Embedded Development Kit
    (EDK)
  • Play with the demos that were delivered with the
    boards
  • Made LED On/Off via RS232 system, using PowerPC
    core Peripherals.

12
PowerPC Hello World System
  • PPC-Core
  • PLB Arbitter
  • PLB BRAM Controller
  • BRAM
  • PLB 2 OPB Bridge
  • OPB Arbitter
  • Processor Reset
  • UART-Lite
  • JTAG PPC controller
  • Xilinx
  • XC2VP7FF869-6
  • PPC405s
  • 1 out of 1 100
  • RAMB16s (2 KByte each)
  • 16 out of 44 36
  • Number of SLICEs
  • 826 out of 4928 16

13
Conclusions
  • Design can easily be ported from Altera to Xilinx
  • RocketIO
  • GOL Receiver is working.
  • Inter FPGA link to be tested.
  • PowerPC
  • Consumes FPGA resources (probably need a XC2VP20
    instead of a XC2VP7 device)
  • Needs investment in learning EDK
  • Needs investment in software development
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