Control Unit

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Control Unit

• ECE-445
• Computer Organization
• Dr. Ron Hayne
• Electrical and Computer Engineering

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Control Unit
MEM
MAR
MDR
Control
PC
R0
R1
IR
...
ALU
Rn-1
Processor
MAR - Memory Address Register MDR - Memory Data
Register
PC - Program Counter IR - Instruction Register
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Fetch and Execute
MOVE NUM1,R1

• Fetch
• MAR ? PC
• PC ? PC 1
• MDR ? MEM(MAR)
• IR ? MDR

• Execute
• MAR ? NUM1
• MDR ? MEM(MAR)
• R1 ? MDR

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Single-Bus Architecture
BUS A
MAR
PC
MEM
MDR
1
2
IR
1
2
MUX
MUX
2
Y
1
1
REGS
A
B
ALU
R
Z
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Instruction Execution

• Perform one or more of the following operations
  in some specified sequence
• Transfer a word of data from one processor
  register to another or to the ALU
• Perform an arithmetic or logic operation and
  store the result in a processor register
• Load the contents of a given memory location into
  a processor register
• Store a word of data from a processor register
  into a given memory location

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Memory Timing

• MOVE NUM1,R1
• 1. MAR ? NUM1
• 2. MDR ? MEM(MAR)
• 3. R1 ? MDR

• One Clock Cycle
• ? Clock Cycles
• One Clock Cycle

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Memory Detail
MEM
MAR
BUS_A
REG
ADDRESS
DATA_OUT
DATA_IN
Enable_Out
Enable_In
CLK
RAM
Write
Enable_In1
Enable_Out2
DATA_OUT
Read
DATA_IN1
DATA_OUT2
REG_2PORT
DATA_IN
DATA_OUT1
DATA_IN2
MFC
Enable_Out1
Enable_In2
CLK
CLK
MDR
MFC Memory-Function-Completed
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Memory Timing
Step RTN Control Signals
1 MAR ? NUM1
2 MDR ? MEM(MAR)
3 R1 ? MDR
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Memory Timing
Step RTN Control Signals
1 MAR ? NUM1 MAR_En_In, IR_En_Out1
2 MDR ? MEM(MAR) MEM_Read, MDR_En_In1, Wait MCF
3 R1 ? MDR MDR_En_Out2, REGS_Sel, REGS_Write
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2
3
Step
1
Clock
MAR_En_In
Address
MEM_Read
MDR_En_In1
Data_Out
MFC
MDR_En_Out2
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Another Example
ADD (R3),R1

• Fetch
• MAR ? PC
• PC ? PC 1
• MDR ? MEM(MAR)
• IR ? MDR

• Execute
• MAR ? R3
• MDR ? MEM(MAR)
• Y ? R1
• Z ? Y MDR
• R1 ? Z

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Control Signals
ADD (R3),R1
Step RTN Control Signals
1 MAR ? PC,PC ? PC 1
2 MDR ? MEM(MAR)
3 IR ? MDR
4 MAR ? R3
5 MDR ? MEM(MAR),Y ? R1
6 Z ? Y MDR
7 R1 ? Z
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Control Signals
ADD (R3),R1
Step RTN Control Signals
1 MAR ? PC,PC ? PC 1 MAR_En_In, PC_En_Out,PC_Inc
2 MDR ? MEM(MAR) MEM_Read, MDR_En_In1
3 IR ? MDR MDR_En_Out2, IR_En_In1
4 MAR ? R3 MAR_EN_In, REGS_Sel, REGS_Read
5 MDR ? MEM(MAR),Y ? R1 MEM_Read, MDR_En_In1, REGS_Sel, REGS_Read, Y_En_In1
6 Z ? Y MDR Y_En_Out1, MDR_En_Out2, ALU_Op Add, Z_En_In
7 R1 ? Z Z_En_Out, REGS_Sel, REGS_Write
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Branch Instructions

• MOVE N,R1
• MOVE NUM1,R2
• MOVE 0,R0
• LOOP ADD (R2),R0
• ADD 1,R2
• ADD -1,R1
• BGTZ LOOP
• MOVE R0,SUM
• HALT

• BGTZ -4
• ? PC

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Branch Instructions
BGTZ LOOP

• Execute
• if CCgt0, PC ? PC IR

• Condition Code
• Z 0, N 0

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Multiple Bus Architecture
BUS A
BUS B
BUS C
PC
IR
1
1
2
A1
A2
1
REGS
2
2
MUX
A
ALU
R
B
NZVC
2
MDR
2
3
1
MAR
MEM
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Example Revisited
ADD (R3),R1

• Fetch
• MAR ? PC
• PC ? PC 1
• MDR ? MEM(MAR)
• IR ? MDR

• Execute
• MAR ? R3
• MDR ? MEM(MAR)
• R1 ? MDR R1

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Control Signals
ADD (R3),R1
Step RTN Control Signals
1 MAR ? PC,PC ? PC 1
2 MDR ? MEM(MAR)
3 IR ? MDR
4 MAR ? R3
5 MDR ? MEM(MAR)
6 R1 ? MDR R1
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Control Signals
ADD (R3),R1
Step RTN Control Signals
1 MAR ? PC,PC ? PC 1 MAR_En_In, PC_En_Out, ALU_Op Pass_B, PC_Inc
2 MDR ? MEM(MAR) MEM_Read, MDR_En_In1
3 IR ? MDR MDR_En_Out2, IR_En_In1,ALU_Op Pass_A
4 MAR ? R3 MAR_EN_In, REGS_Read1,ALU_Op Pass_A
5 MDR ? MEM(MAR) MEM_Read, MDR_En_In1
6 R1 ? MDR R1 MDR_En_Out2, REGS_Read2,ALU_Op Add, REGS_Write
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Questions?