BDDbased Logic Synthesis for FPGAs

1
BDD-based Logic Synthesis for FPGAs

• Presented by
• Kesava R. Talupuru

2
Outline

• BDS system over all flow
• BDD Store/Load mechanism
• Algorithm for Decomposition
• Construction and Processing of factoring trees
• Complete synthesis flow example in BDS
• Project Status

3
Synthesis flow of BDS
Boolean Network
Construct Global BDDs
BDD decomposition Engine
Construct One Node on the Factoring Tree
N
BDD has one
Node ?
Y
Factoring Tree Processing
Synthesis Result Presentation
Technology Mapping
4
BDD Store/Load Mechanism
Storage in BDD pool
Original BDD
F
F
Index 61 Dd NULL
a
61
4862
b
Index 4862 Dd NULL
Index 61 Dd NULL
c
4867
1
Index Const.
5
Reconstruction of BDD from the BDDPool
F
a
61
Index 61 Dd
4862
b
4867
c
Index 4862 Dd
1
Index 4867 Dd
b
c
c
Index Const.
1
1
6
BDD-based Functional Decomposition

• Theory of Dominators forms the basis

7
Main BDD decomposition flow

• bddPool storeBdd (bdd)
• Enqueue (Q, bddPool)
• while (bddPool Dequeue (Q) )
• f localBdd (bddPool)
• (g, h, op) decomposeBdd (f)
• construct one node on factoring tree
• if (g ! single node)
• gPool storeBdd (g)
• Enqueue (Q, gPool)
• if (h ! single node)
• hPool storeBdd(h)
• Enqueue (Q, hPool)
• Return (factoring tree )

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BDD Decomposition algorithm

• decomposeBdd (f)
• structure bddScan (f)
• done decompSimpleDominator (f, g, h, op,
  structure)
• if (done) return (g, h, op)
• bddVariableReorder ()
• done decompSimpleDominator (f, g, h, op,
  structure)
• if (done) return (g, h, op)
• done decompFunctionalMux (f, g, h, op,
  structure)
• if (done) return (g, h, op)
• done decompSingleMux (f, g, h, op,
  structure)
• if (done) return (g, h, op)
• done decompGeneralizedDominator (f, g, h,
  op, structure)
• if (done) return (g, h, op)
• done decompGeneralizedXDominator (f, g, h,
  op, structure)
• if (done) return (g, h, op)
• cofactoringWithTopVar (f, g, h, op)
• return (g, h, op)

9
Construction and Processing of Factoring Trees
d
e
g
f
d
f
e
g
c
a
a
c


b
b
b
a
b


c
c
b
b
a
Original BDD
Factoring Trees
1
10
Construction and Processing of Factoring Trees
d
f
e
g
c
c



Factoring Trees after sharing extraction
b
a
b
c
11
Complete Synthesis Example
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Complete Synthesis Example contd
Decomposition of BDD g
13
Complete Synthesis Example contd
Decomposition of BDD h
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Complete Synthesis Example contd
Sharing Extraction on the factoring trees of g
and h
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Work done and to be done

• Decompositions targeting FPGAs is successfully
  completed
• Need to take care of dumping the blif file for
  gates which have more than two inputs
• Use flow map tools to map onto FPGAs
• Compare the results between original BDS and
  BDS-pga in terms of LUTs