Motorola PowerPC Microprocessors

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Motorola PowerPC Microprocessors

• Dr. Doug L. Hoffman
• Computer Science 330
• Spring 2000

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Superscalar Microprocessor

• The PowerPC 620 microprocessor is a 64-bit
  implementation of the PowerPC(TM) Reduced
  Instruction Set Computer (RISC) architecture.
• technical and scientific work-stations
• application and LAN servers
• symmetric multiprocessing computer systems.
• software compatible with the PowerPC 601, 603,
  and 604 microprocessors.

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Superscalar Microprocessor

• The PowerPC 620 microprocessor is a superscalar
  design capable of issuing four instructions per
  clock cycle to six independent execution units,
  including
• Two single-cycle integer units.
• Multicycle integer unit.
• Branch Processing unit.
• Load/Store unit.
• Floating-point unit.

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Hazard Avoidance Features

• Dynamic branch prediction.
• Speculative execution through four unresolved
  branches.
• Multiple execution units.
• Out-of-order execution with in-order instruction
  completion.

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Cache and MMU Support

• The PowerPC 620 microprocessor has separate
  32-Kbyte instruction and data caches.
• Both caches are 8-way set-associative.
• 128-bit Level 2 cache interface provides support
  for Level 2 caches of 1 Mbyte in size.

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Address translation

• 128-entry translation lookaside buffers (TLB).
• support for demand-paged virtual memory
  management for both page- and variable-sized
  blocks.
• Several interesting addressing modes and
  instructions (indexed, bc for loops).

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Functional Unit Organization
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PowerPC 620 Microprocessor Major Features Summary

• Technology
• 3.3-volt implementation
• 0.5-micron static CMOS technology
• 311 mm2
• 7.0 million transistors

• Specifications
• 32K instruction and 32K data caches
• Superscalar--up to 4 instructions per clock
• Dynamic branch prediction
• Multiple integer units
• 128-bit data bus
• Separate L2 cache interface
• 128-bit L2 data bus

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MPC7400 Microprocessor

• The MPC7400 PowerPC microprocessor with AltiVec
  technology integrates a traditional scalar
  processor with a fully independent
  vector-processing engine on a single copper
  technology based chip.

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Feature Highlights

• 128 but Vector Execution Unit.
• AltiVec vector unit can execute up to 20
  operations per clock cycle.
• 162 new instructions (so much for RISC).
• manufactured with the new .15-micron copper
  HiPerMOS fabrication process.

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Vector Execution Unit
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Vector Execution Unit

• 32 new vector registers.
• Registers 128 bits wide.
• Single Instruction, Multiple Data (SIMD)
• Processes up to 16 pieces of data with one
  instruction.
• Vector Permute Function.

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Vector Execution Unit

• Short vector parallel architecture.
• Vectors are 4, 8 or 16 elements long, depending
  on data size.
• 16-way parallelism for 8-bit signed and unsigned
  integers and characters.
• 8-way parallelism for 16-bit signed and unsigned
  integers.
• 4-way parallelism for 32-bit signed and unsigned
  integers and IEEE floating-point numbers.

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Applications of AltiVec Technology

• The initial target applications for PowerPC
  processors utilizing AltiVec technology include
• IP telephony gateways
• Multi-channel modems,
• Speech processing systems
• Image and video processing systems
• Scientific array processing systems
• Internet routers
• Virtual private network servers.

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The Last Word

• So fast the government classified it as a
  munition for export purposes.
• I really want one!!!!