Clock Buffer Polarity Assignment for Power Noise Reduction

1
Clock Buffer Polarity Assignment for Power Noise
Reduction

• Rupak Samanta, Ganesh Venkataraman and Jiang Hu
• Department of Electrical and Computer Engineering
• Texas AM University

2
Outline

• Introduction
• Motivation
• Problem Description
• Polarity Assignment Algorithm
• Buffer-type Selection and Post Processing
• Results and Summary

3
Introduction

• Power/Ground noise is a major source of VLSI
  Circuit timing variation
• 10 power noise may cause 29 inverter delay
  variation in 45nm technology (S.Sapatnekar et.al,
  IEEE Design and Test 2003)
• A main culprit of power noise is the clock
  network
• Buffers in the clock tree switch simultaneously,
  thereby induce power/ground noise
• It is imperative to separate the simultaneous
  switching of clock buffers
• We have proposed a fine-grain signal polarity
  assignment of clock buffers

4
Previous Work on Buffer Signal polarity Assignment

• Y.-T.Neih et.al, Minimizing Peak Current via
  Opposite-Phase Clock TreeDAC05

5
Previous Work

• Both signal polarities can be accommodated by
  using different types of Flip-Flops

6
Limitation Local Power Noise reduction

• The approach faces dilemma in two scenarios

7
Impact to Delay Variation
(b)
(a)
(c)
8
Delay Variation

• According to L. H. Chen et.al, Buffer delay
  change in presence of power and ground
  noiseTVLSI03

• A,B, C, D are gt 0
• Case (a) has more rising delay increase and less
  falling delay increase
• Case (b) has less rising delay and more falling
  delay increase
• Case (c) has common mode noise zero, thus there
  is less increase in delay variation.
• Thus clock buffer polarity assignment can reduce
  the delay variation

9
Problem Description

• Given a buffered clock tree with n buffers
• Objective Assign either positive or negative
  signal polarity to each buffer
• The difference in number of positive buffers and
  the number of negative buffers is no greater than
  1 in a local region

• We have used 3 different Algorithms
• Partitioning
• 2-Coloring of Minimum Spanning Tree (MST)
• Recursive Min-Matching

10
Polarity Assignment Algorithms
11
Technique 1 Partitioning

• A graph G (V,E) is formed out the buffered
  clock tree
• The buffers form the nodes of the graph
• Edge weight is defined the distance between two
  nodes

V-
V
V
V-
Bi-partition Algorithm
V
V-

• V and V- corresponds to positive and negative
  polarities
• We have and
• The two nodes with small edge weight are more
  likely to be in two different sets

12
Technique 2 2-Coloring of MST
V-
V
Find Minimum weighted edge
V-
V-
V
V
V
V-
V-
V-
V
13
Technique 3 Recursive Min-Matching
V-
V
V
V-
Min-matching Algorithm
V-
V
V-
V
Min-matching Algorithm
V-
V-
V
V-
V
V
V
V-
V
V-
14
Buffer Type Selection and Post Processing
15
Buffer Type Selection

• We need to chose either inverting or
  non-inverting type for each clock buffer

Clock Source
V
V-
V
V-
V
V
V-
Positive Edge-triggered FF
Positive Edge-triggered FF
Negative Edge-triggered FF
16
Buffer Type Matching
Clock Source
Non-Inverting Buffer
Clock sink (flip-flop)

• The buffer type matching is done on a pair of
  sequentially adjacent (SA) FFs i and j at a time
• Two FFs are sequentially adjacent if there exists
  a combinational path between them
• Mismatch score that is sum of products of
  criticality and number of mismatched buffers
  between each sink pairs
• Criticality depends upon the timing constraint
  and distance between respective pairs of FFs

17
Buffer Type Matching contd..
Calculate MismatchScore(MS_G)
Chose the most critical sink pairs
No
Find the mismatch buffer types
Calculate MismatchScore(MS_U)
No
If MS_U lt MS_G MS_G MS_U, Valid Swap
Correct the polarity of downstream buffers
No Valid swap, EXIT
STOP
18
Clock Skew Tuning

• Clock skew is changed due to change in buffer
  type in polarity assignment
• The tuning procedure is same as in, G.
  Venkataraman et.al, ICCAD05
• Dummy capacitors are added to the buffers and
  are tuned towards desired clock skew

Dummy Cap
19
Results and Summary
20
Experimental Set-up

• The proposed procedure was implemented in C in an
  Windows environment having a 1GB RAM
• The initial clock trees were obtained using
  ISCAS89 benchmarks
• The circuit was synthesized and technology mapped
  using SIS
• The position of clock sinks were obtained in mPL.
  The clock tree was generated using G.
  Venkataraman et.al, ICCAD05
• We used 180nm technology file

21
Peak Current
22
Power Noise
23
Delay Variation
24
Result Discussion

• The reduction in peak current is significant
  38-44
• The power supply noise variation come down by
  44-50
• The delay variation reduction is 50-54. For one
  benchmark the 2-Coloring algorithm led to a
  reduction in delay variation of 75
• The skew for the three different algorithms are
  reduced to the base case
• The run time of the three approaches are in few
  seconds
• Thus our technique offers the flexibility of
  trying all three approaches and pick the one that
  offers best result

25
Summary

• Contribution
• Proposed techniques to reduce the clock network
  induced power supply noise by assigning different
  polarities to clock buffers in existing clock
  tree
• Three different algorithms were detailed for the
  same problem
• Buffer type matching and clock skew tuning was
  carried out as a post processing step
• Conclusion
• Experimental results indicate significant
  reduction in peak current, power supply noise and
  delay variation
• Such reductions in peak current and delay
  variation lead to more robust circuit

26
Thanks!
Questions ?