Studio Session 1: Introduction to VHDL and related Tools

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Studio Session 1 Introduction to VHDL and
related Tools

• EE19D 25/01/2005

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Topic

• Definitions
• Visual Introduction of VHDL using EVITA
  (www.aldec.com)
• Getting started with Xilinx ISE Tool
• Simulation of VHDL Models with Moldelsim

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Definition of an HDL

• Def A high level programming language used to
  model hardware.
• special hardware related constructs
• digital (now) and analog (near future)
• models used for documentation, simulation,
  synthesis, and test generation
• have been extended to the system design level

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Language Semantics

• Semantics what is the meaning of a language
  construct?
• HDLs have different semantics for different
  applications
• Simulation
• Synthesis
• Test
• In this course we will be concerned with
  simulation and synthesis semantics.

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VHDL

• VHDL VHSIC Hardware Description Language
• VHSIC Very High Speed Integrated Circuit
  Program
• DOD began development in 1983
• design exchange among VHSIC contractors
• document parts with long functional life
• IEEE Standardization
• Standardization process began in 1985
• IEEE Standard 1076 in 1987
• Updated in 1993

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Significance of VHDL

• VHDL provides a text based approach to structured
  hardware modeling and design.
• Analogous to high level software languages such
  as PASCAL, C, C, and JAVA.
• An important tool in managing the complexity of
  VLSI systems.

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Why Use VHDL?

• Reason 1 it allows textual design
  representation
• Reason 2 Ability to model at different levels
  of abstraction

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Abstraction Levels
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SILICON LEVEL
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CIRCUIT LEVEL
Inverter
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GATE LEVEL
Flip Flop
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REGISTER LEVEL
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CHIP LEVEL
RAM
µ
8
8
P
Par.
Port
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USART
Int.
Con.
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SYSTEM LEVEL
IMU
A/B Computer
RADAR
C/D
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• VHDL Provides total modeling capability at the
  gate level, register level, and chip level.
• It can also be used in many applications at the
• system level
• circuit level
• Switch level (gate-circuit hybrid)

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Reason 3 Design Decomposition
VHDL supports very naturally the Design
Decomposition process.
behavioral model
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Reason 4 Design Validation

• VHDL can be used to validate design at a high
  level, thus detecting errors early in the
  design process
• Important, because finding errors later is
  expensive