Title: Front-end Electronics for the LHCb Preshower R
1Front-end Electronics for the LHCb
PreshowerRémi CORNAT, Gérard BOHNER, Olivier
DESCHAMPS, Jacques LECOQ, Pascal PERRETLPC
Clermont-Ferrand
2Plan
- Introduction
- Front-end Electronics
- Very front end
- Front end
- Prototypes
3The Preshower
- Located upstream from ECAL
- 6000 cells (same as ECAL)
- 12 mm thick lead plane followed by scintillator
pads
ADC
Front-end
4Raw Signal
- We mostly have MIPs
- 1 MIP signal is very erratic
- Longer than 25 ns
- 85 during 1st period
- ?
- Dynamic range from 0 to 100 MIP
- Trigger at 5 MIP (5 accuracy)
- 10 bits
5Very Front-end Electronics
- Common mode to differential mode conversion
- Signal integration
- Within 25 ns periods
- Without dead-time
- 16 half-channels per chip
- 2 V amplitude
6Cable adaptation
- Standard CAT5 Ethernet cable
- No individual but common shielding
- Both sides adaptation
- Pole-zero correction
- No significant crosstalk
- Negligible reflected signal after 20 m long
7Front-end Electronics
- Mixed part
- Signal reception
- Levels adaptation
- Digitisation
- Digital processing
- Physics data
- Trigger data linked to SPD and ECAL
8FEE Mixed part
- Everything in differential mode from VFE to
digitisation - Cable adaptation
- Electrical levels matching
- From 1 V positive differential, -0.8 V CM to 1V
bipolar differential, 0.5 V CM - Op. Amp. AD8138 or AD8132
- 50 mV differential pedestal
- To cancel VFE offset
- Low pass filter
- Noise reduction
9FEE Mixed part
- Digitisation AD9203
- 10 bits, 40 MHz, 75 mW,
- differential inputs
- Package size fits requirements
- (64 channels on the FE board)
- Vref feed-back from ADC
- to Op. Amp.
- RJ 45 connector
-
10FEE Mixed part
11FEE Mixed part
- 1 cm x 4 cm hierarchical element
- 64 channels fit on a 9U board
- Noise from 0.8 mV to 0.4 mV
- due to layout optimisation
- Ground plane
- Critical wires routing
- LVDS Clock
12Digital Processing
- Pedestal
- Gain
- Pile-up
- PMT signal longer than 25 ns
- Coding (float, 8b)
- Parameters per half channel
- 128 half-channels per board
13Trigger data
- SPD data
- 64 bits per FE board
- Preshower 1 bit per cell
- Threshold on PS processed data
14Trigger functions
- Trigger data 1b (threshold)
- SPD data processing count hits in a 64 b data
block - FPGA 1 clk cycle
- Neighbourhood search
- Dedicated prototype, tested and validated
15Trigger functions
- SPD data synchronization
- Time alignment with respect to PS data
- Multiplicity calculation on SPD data
- Neighbours fetch
- 2x2 algorithm
- 1 address per ECAL FE
- board (half PS FE board)
- Send only useful data to
- ECAL validation board
16Neighbours
- Process applied on both SPD and PS data
- Data multiplexed to outputs according to the
address - The structure for 1 half-board fits into an
EPM3256 - tp_at_-gtout lt 20 ns
- Low level vhdl model written
- Prototype tested
- Will be fitted into ACTEL fpga
17SPD
- SPD data synchronization
- Variable length pipe-line
- Multiplicity calculation on SPD data
- Count hits in a 64 bits data block
- Low level VHDL model written
- FPGA one 40 MHz clock cycle (Altera ACEX)
18FE boards synchronization
- Bordering cells data transmitted between PS FE
boards - Latency for neighbours transmission depends on
data source - Local board
- N, E board
- Corner board
- Pipe-line stages added to compensate
19FPGA based prototype
- 16 channels 2 VFE chips
- No TTC, no ECS
- Additional DAQ system
- FPGA internal memory
- VME
- Was used for test beam
- with PS detector and VFE
- chip prototypes
20FPGA based prototype
- DAQ channel L0 pipe-line RAM
- Up to 1024 samples per run (internal memory
limitation) - Single and temporal modes
- Allows to acquire up to 32 successive samples per
trigger - Many process and acquisition parameters
- C software ROOT graphical interface
- LabView version for debugging purpose
21Graphical interface
- Linux
- Statistical
- analysis
- Can manage
- many boards
22ASIC prototype
- 4 channels (design is pad limited)
- AMS 0.35 mm
- 9 mm2
- CQFP100 package
- 220 configuration bits through
- a serial interface
- Parity check and triple voting on configuration
data - Will be tested soon
23Approximate cost
- 4 channels 1 ACEX1K or 1 9mm2 ASIC or ½ ACTEL
SX32 - 32 cm in height for 64 channels
- Foundry and design delays ? subcontracted ACTEL
prog. - ASIC meets available space constraints on the
board
Technology Ch. , package Cost/channel
ACEX1K100 4 (6), QFP208 10 EUR (/1000) ECS
ASIC 0.35 ?m 4, QFP100 12 EUR (/2000) test
ACTEL 54SX32 2, QFP208 18 EUR (/1000) progtest
24Conclusion
- VFE FE validated (test beam)
- Low noise for the analogue part
- (Radiation and) surface use constraints
- Best candidate ASIC
- Prototype board used for MAPMT characterization
- Final board
- Collaboration with LAL (Orsay) DAQ, ECS, TTC
parts