Front End Electronics for the SPD of LHCb

1
Front End Electronics for the SPD of LHCb

• Electronics in Experimental High Energy Physics
• Xavier Vilasís-Cardona
• Enginyeria i Arquitectura La Salle
• URL - Barcelona

2
The collaboration in Barcelona

• Universitat de Barcelona
• Lluis Garrido
• Ricardo Graciani
• David Gascón
• Ernest Aguiló
• Miriam Calvo
• Sergio Gómez
• Sebastià Bota
• Atilà Herms
• Angel Diéguez
• Xavier Cano

• Enginyeria i Arquitectura La Salle
• Rafael Ballabriga
• Sonia Luengo
• Mar Roselló
• Jordi Riera
• Xvc

3
Outlook

• What is LHC ?
• What is LHCb ?
• The SPD
• Photomultipliers
• Very Front End Electronics
• The ASIC
• Front End Electronics

4
LHC the future collider at CERN

• Proton-Proton
• Starting 2007
• Find the Higgs
• Find new physics
• 4 detectors
• Alice
• Atlas
• CMS
• LHCb

5
LHC some data

• Energy at collision 7 TeV (1700 TeV for ions)
• Dipole field at 7 TeV 8.3 T
• Bunch spacing 7.5 m
• Bunch separation 24.95 ns
• Particles per bunch 1011
• Current 0.56 A
• Luminosity 1034 cm2 s
• Energy per beam up to 0.35 GJ
• Stored magnetic energy up to 1.29 GJ per sector
• TOTAL STORED ENERGY 11 GJ

6
LHCb

• A single-arm spectrometer covering
• ?min 15 mrad (beam pipe and radiation)
• ?max 300 mrad (cost optimisation)
• Precise measurements of CP violation
• B mesons
• CKM matrix elements

7
LHCb what is CP violation ?

• CPT is an exact symmetry
• C charge conjugation
• P parity
• T time reversal
• CP is almost exact
• CP violation explains matter-antimatter asymmetry

8
LHCb the trigger

• LHCb 1000k channels too much data
• The multi-level trigger chain
• Logging rate 200 Hz (20 MB/s) 200 TB/year
• All LHC experiments 5-8 PB/year

9
SPD

• Scintillator Pad Detector
• In front of the calorimeter
• Discriminates photons from electrons at level 0
  of trigger

10
SPD structure

• 6000 Scintillator Pads
• Helicoidal WLS optic fibers
• 64 channel PMT (Hamamatsu)
• 1 bit per channel at 40 MHz
• Synchronisation issues

• Send bit to PreShower
• Compare to a variable threshold
• Radiation hard

11
SPD signal shape

• Few photoelectrons
• Irregular signal shape
• Extended over 25 ns
• Non-uniform PMT gain

12
SPD electronics design
13
ASIC why an ASIC ?

• 6000 channels minimal area /ch
• Processing speed 40 MHz
• Power consumption lt 2 W / 64 channels
• Analog Processing Digital Control
• Signal range. 0 to 5 MIP (0 to 650 mV)
• Electronics resolution 5 of 1 MIP
• Dynamic range 40 dB (7 bits)

14
ASIC Structure
15
ASIC characteristics

• Programmable
• Thresholds per sub-channel
• Subtraction from 0 up to 40 of the signal
• T0 done externally with a delay unit (LAL
  design)
• 0.8 ?m AMS BiCMOS Technology
• Dual channel
• Fully differential
• Working at 3.3V
• SEU and SEL protection
• Triple voting
• Guard rings

16
Review of ASIC runs

• RUN1 (Sep 2000)
• Test separate blocs
• 1 full channel
• RUN2 (Jun 2001)
• 4 full channels
• ECL vs CMOS output
• RUN3 (Jan 2002)
• New tunnable substractor
• 1 full channel with digital control
• On-chip DAC to program thresholds
• RUN4 (Sep 2002)
• 1 Complete processing channel
• Separate blocs digital control
• Works at 3.3 V to reduce power consumption
• Fully differential preamplifier added before the
  integration stage to meet PMT DC current limit
  requirements

17
ASIC RUN 4 layout
18
ASIC integrator
19
ASIC Track and Hold
20
ASIC substractor
21
ASIC latched comparator
22
ASIC integrator measurements
10 circuits

• Offset (Output Zero Error) ltOZEgt 38.6 mV
  ?io 70 mV r.m.s.
• Gain ltVo/Vigt 16.51 (for a typical input
  pulse) ?io 0.091 r.m.s. (0,55)
• Treset 5.5 ns (for 1 V output)
• Noise Eno lt 2 mV r.m.s (Using scope, C.F. 6)
• Eno lt 1 mV r.m.s (Discriminator sweep of
  thresholds)

23
ASIC integrator linearity
24
ASIC programmable substractor
25
VFE Board description

• 100 boards
• 7x12 cm
• Multiplexed LVDS

26
Very Front End Board
Test beam boards

• Sep 2001 RUN 2, 4 full channels/ 4-layer board
• ECL vs CMOS output
• Clock signal distribution
• Power Supply distribution
• June 2002 RUN 2, 4 full channels / 4-layer board
• Improvements in board design
• Signals distribution
• June 2002 RUN 3, 1 full channel and digital
  control/ 6-layer board
• Digital signal distribution vs analog signal
  distribution
• Noise effect vs number of layers

27
Front End Board

• Control Unit
• Bus Bridge
• Programmable Delays

1 Control Unit every 4 VFE Boards 5 Control Units
in a Front End Board 6 Front End Boards
28
Conclusions