To verify the structure

1
To verify the structure

• Easy to hook together combinationals and
  flip-flops
• Harder to make it do what you want

2
To verify the structure

• We want to check
• Does my structure contain combinatorial loops?
• We want to compute
• What values are being computed
• by the structure right now? (simulation)
• We will need to estimate
• How fast can we clock this structure (timing
  analysis)

3
To verify the structure

• These three problems are all related to each
  other
• The underlying concepts are graphtheoretical
• We use topological sort

4
Answer

• Impossible to be sure by inspection
• We need a procedure

5
Where do we begin?

• ...... At the primary inputs
• But ...
• What is an input to the circuit?

6
Inputs

• Heres one!
• Its a break. There is nothing upstream
• As far backwards as we can go

7
Is there a path through this?
8
The D- flip flop

• Combinationally, the D-flip flop is like this

9
Zero ext.
Branch logic
0
A
ALU
4
B

31

Sgn/Ze extend
10
A

Add one
-
Left shift one bit
Equal?
11
B

Add one
-
Left shift one bit
Equal?
12
The procedure
Visit_line (p) Mark line For each
component connected Visit_component
(p) End
Visit_component (q) Mark input save q
If all inputs marked then Calculate
output For all outputs Visit_line
(output) End
Main For all inputs Visit_line
(value) If all lines visited then OK
Else Combinatorial loop End
13
A

Add one
-
Left shift one bit
M
Equal?
14
A

M
Add one
-
Left shift one bit
M
Equal?
15
A

M
Add one
-
Left shift one bit
M
M
Equal?
16
A

M
M
M
Add one
-
Left shift one bit
M
M
Equal?
17
A
M

M
M
M
M
Add one
-
M
Left shift one bit
M
M
Equal?
18
A
M
M
M

M
M
M
M
Add one
-
M
Left shift one bit
M
M
Equal?
19
A
M
M
M
M
M
M
M

M
M
M
M
Add one
-
M
Left shift one bit
M
M
Equal?
20
A
M
M
M
M
M
M
M

M
M
M
M
Add one
-
M
Left shift one bit
M
M
M
Equal?
M
21
B

M
Add one
-
Left shift one bit
M
M
Equal?
22
B

M
M
M
Add one
-
Left shift one bit
M
M
Equal?
23
B
M
M

M
M
M
Add one
-
Left shift one bit
M
M
Equal?
24
B
M
M
M

M
M
M
Add one
-
Left shift one bit
M
M
M
Equal?
M
25
B
M
M
M

M
M
M
Add one
-
Left shift one bit
M
M
M
Equal?
M
26
Static timing analysis

• Use the topological sort procedure
• Use max delay as component output

27
A
15
0
0
26
0
0

32
Add one
20
-
8
18
0
Left shift one bit
Equal?
28
A
15
0
0
26
0
0

32
8
Add one
20
-
8
18
0
Left shift one bit
8
0
Equal?
29
A
15
0
0
26
0
0

0
20
32
8
Add one
20
-
8
18
0
Left shift one bit
8
0
Equal?
30
A
15
0
0
26
0
40
0

40
32
0
20
8
Add one
20
-
0
8
18
0
8
Left shift one bit
0
Equal?
31
A
15
0
0
0
0
26
0
40
0

40
32
0
20
8
Add one
20
-
0
8
18
0
8
Left shift one bit
0
Equal?
32
A
15
0
0
0
15
0
0
26
0
55
40
0
81

40
32
0
20
8
Add one
20
-
0
8
18
0
Left shift one bit
8
26
0
Equal?
0
33
A
0
15
81
40

Add one
-
26
Left shift one bit
Equal?
34
Compiled simulation

• Use the topological sort procedure
• Use logic function as component output

35
A
4
7
11
5

Add one
-
1
Left shift one bit
Equal?
36
A
4
7
11
5

2
Add one
-
1
Left shift one bit
2
1
2
Equal?
37
A
4
7
11
5

5
6
2
Add one
-
1
Left shift one bit
2
1
2
Equal?
38
A
4
7
11
-9
5

5
-9
6
2
Add one
-
11
1
Left shift one bit
2
1
2
Equal?
39
A
4
7
7
7
11
-9
5

5
-9
6
2
Add one
-
11
1
Left shift one bit
2
1
2
Equal?
40
A
4
7
7
4
7
4, Propagate NEG INPUT
POS
4
NEG
11
4
-9, N1
5
10
10

5
-9
6
2
Add one
-
11
1
Left shift one bit
2
0
1
2
Equal?
4
41
A
7
4
10
-9

Add one
-
0
Left shift one bit
Equal?