CSIS 3510 Computer Organization and Architecture

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CSIS 3510 Computer Organization and Architecture

• S-R Latch, from two NOR gates.
• S Set input to top NOR
• R Reset input to bottom NOR
• Race conditions when SR1 goes to SR0
• Indeterminate outcome

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Solve the SR1 problem

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Another S-R FF

• Edge-triggered S-R Flip Flop
• Circuit (a) produces a momentary clock pulse
• Length of the pulse is determined by delay of the
  invertor before b changes
• Short clock pulse allows control of input timing

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Packaging D Gates in Chips

• This chip has 14 pins, including V and GND.
• Two D FFs in a single package
• Includes D, Q, not-Q, and Clock (CK)
• Also Preset (PR) sets to 1 regardless of D
• Also has Clear (CLR) which resets to zero
• A simple integrated circuit

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Packaging D gates

• Larger scale of integration (almost 100
  transistors)
• Access to Q, D, on each chip
• CK and CLR are ganged together
• Stores a single byte of data (8 bits, one per D
  FF)

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4 X 3 Memory

• 4 words of memory
• 3 bits per word
• Decoder selects word, based on A1 and A0 (two
  address lines) on the left of the diagram
• Three data lines in (on top)
• Three data lines out (on bottom)
• Common Chip-Select and RD lines
• Output-Enable line (lower right) controls
  tri-states to the bus

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Alternative Memory Organization

• Two ways to organize the same amount of memory
  (4M bits)
• Right diagram (4096K x 1) needs 22 address lines
  (4 M addresses)
• Address is read in two phases (11 bits each
  phase) slower memory
• Note different numbers of pins needed for each
  design

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Memory Design Problem

• Ram chips have 28 pins
• Need 1M addresses of 16 bits
• As usual, need V, GND, R/W, Chip-Select
• Determine the best organization. Explain/justify
  your answer and show all your work.
• Draw a schematic diagram of your solution

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Addr Data Mem Org Bits/Chip Chips for Word Words for Addr Total Chips
23 1 223 X 1 8M X 1 8M 16 1 16
22 2 222 X 2 4M X 2 8M 8 1 8
21 3 221 X 3 2M X 3 6M 6 1 6
20 4 220 X 4 1M X 4 4M 4 1 4
19 5 219 X 5 512K X 5 2.5M 4 2 8
18 6 218 X 6 256k X 6 1.5M 3 4 12
17 7 217 X 7 128K X 7 896K 3 8 24
16 8 216 X 8 64K X 8 512K 2 16 32
The 1M X 4 organization minimizes chip count,
with no unused bits on the chip. A single bank
is required, so no decoder will be needed.
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