Cosynthesis and Its Integration With C to VHDL Converter

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Cosynthesis and Its Integration With C to VHDL
Converter

• by
• Amarjeet Singh (1998167) Amit
  Chhabra (1998168)

under Prof. M. Balakrishnan
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Presentation Plan

• Introduction.
• Embedded System Group and integration of our
  project with the group.
• Present C to VHDL converter and its limitations.
• Our contribution
• Future work planned

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Motivation

• Automated Hardware/Software Codesign offers
  design methodology for total system.
• Convert critical code segments into hardware
  through synthesizable behavioral VHDL code.

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Objective

• Transformation of part of application identified
  for hardware implementation into synthesizable
  VHDL code.
• Cosimulation with software implemented part to
  validate the application against the estimations.

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ES Project Overview
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Integration with Estimator,Partitioner and
Synthesizer

• Given application has to be estimated and
  partitioned before generating VHDL code which
  then is to be cosimulated.
• Software and Hardware Estimators attach
  annotations taking into account time and type
  considerations.

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Integration with Estimator,Partitioner and
Synthesizer (contd.)

• Partitioner divides the application into software
  and hardware implemented parts.
• Cosimulation of the synthesizable VHDL code with
  the software implemented part to validate the
  estimations.

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Present C to VHDL Converter

• Implements generalized entity for any type of
  procedure.

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Present C to VHDL Converter (contd.)

• Handles the basic C data types (integers, arrays,
  pointers, reference variables).
• Handles the C constructs like if-then-else, for,
  while-do, do-while, arithmetic operations.

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C to VHDL Mapping

• if-then-else if-then-else
• while-do if-then, while-do
• do-while first iteration,
  while-do
  
  
• for-do for-do
• Arithmetic Arithmetic
• operations operations

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Limitations of the Present Converter

• No mutual recursion allowed.
• Hardware to hardware communication not supported.
• The return statement at the end of code should
  return only void or integer.
• Declarative limitations for variables, procedures.

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Our Contribution

• Testing the previously made converter removing
  various bugs, allowing other procedures to be
  called within a procedure.
• Generating the VHDL code for various
  applications implementing the constructs allowed
  in different forms.

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Our Contribution (contd.)

• Simulating the codes generated, through self made
  testbench to validate against the software
  application implemented.
• Integrating the converter with the estimators
  (hardware and software ) and partitioner.

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Our Contribution (contd.)

• Adding random or manual hardware and software
  estimations to test various applications thus
  bypassing the estimators if required.

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Future Work Planned (Converter Extensions)

• Checking the feasibility for adding various other
  C constructs and operations (switch-case, bit
  operations).
• Clock synthesis for enabling the synthesizability
  of VHDL code generated.
• Provision of global memory for all hardware
  mapped procedures.

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Future Work Planned (Cosynthesis and Integration)

• Synthesizing the hardware-software interface.
• Cosimulation to validate the application against
  the estimators.
• Integrating our work with the Embedded System
  group for large application implementation.

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• THANK YOU