Computer Architecture CSE 3322

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Computer Architecture CSE 3322

• Lecture 2

Course WEB SITE http//crystal.uta.edu/jpatter
s/cse3322/index.html
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Why Study Computer Architecture

• Learn to Design Computers
• Processors Designed by Few Semiconductor
  Companies

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Why Study Computer Architecture

• Learn to Design Computers
• Processors Designed by Few Semiconductor
  Companies
• Learn to Design Device Controllers

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Why Study Computer Architecture

• Learn to Design Computers
• Processors Designed by Few Semiconductor
  Companies
• Learn to Design Device Controllers
• Learn to Design More Optimum Software!

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Why Study Computer Architecture

• Learn to Design Computers
• Processors Designed by Few Semiconductor
  Companies
• Learn to Design Device Controllers
• Learn to Design More Optimum Software!
• Learn to Design More Optimum Systems!

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How to Improve Application Performance ?
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How to Improve Application Performance ?

• Algorithm
• Language and Compiler
• Processor and Memory System
• I/O System and Devices

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Computer Generations Overview
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Computer Generations Overview
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Computer Generations Overview
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Computer Generations Overview
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Computer Generations Overview
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Technological Growth

• DRAM Growth
• 4X Capacity Every 3 Years

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Technological Growth

• DRAM Growth
• 4X Capacity Every 3 Years
• Workstation Performance Improvement 54
  per year or 2X every18 months

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Technological Growth

• DRAM Growth
• 4X Capacity Every 3 Years
• Workstation Performance Improvement 54
  per year or 2X every18 months
• Disk Drive Growth
• Capacity More than 2x every year

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Technological Growth

• DRAM Growth
• 4X Capacity Every 3 Years
• Workstation Performance Improvement 54
  per year or 2X every18 months
• Disk Drive Growth
• Capacity More than 2x every year
• All Continue to Drive Price /Performance
  Improvements

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Five Components of Computers
Memory
Control
Input
Datapath
Output
Processor
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Instruction Set Design

• Key Element in the Architecture
• Function, Cost, Performance, etc.

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Instruction Set Design

• Key Element in the Architecture
• Function, Cost, Performance, etc.
• Typical Machine Instructions
• Data Transfers ( reg-reg, reg-mem, mem-reg)
• Arithmetic (add, subtract, multiply)
• Logic String (boolean, bit manipulations)
• Program Control ( branches, jumps)
• Input/Output Operations

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Instruction Set Design
Study the MIPS Architecture
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Instruction Set Design
Study the MIPS Architecture

• A WORD is 32 bits or 4 bytes wide for
• Registers and Memory

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Instruction Set Design
Study the MIPS Architecture

• A WORD is 32 bits or 4 bytes wide for
• Registers and Memory
• Each byte has Memory Address starting at 0

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Instruction Set Design
Study the MIPS Architecture

• A WORD is 32 bits or 4 bytes wide for
• Registers and Memory
• Each byte has Memory Address starting at 0
• WORD Addresses start at 0 and are multiples of 4

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Instruction Set Design
Study the MIPS Architecture

• A WORD is 32 bits or 4 bytes wide for
• Registers and Memory
• Each byte has Memory Address starting at 0
• WORD Addresses start at 0 and are multiples of
  4
• Big-endian Byte 0, Byte 1, Byte 2, Byte 3
• Little-endian Byte 3, Byte 2, Byte 1, Byte 0

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Instruction Set Design
Study the MIPS Architecture

• A WORD is 32 bits or 4 bytes wide for
• Registers and Memory
• Each byte has Memory Address starting at 0
• WORD Addresses start at 0 and are multiples of
  4
• Big-endian Byte 0, Byte 1, Byte 2, Byte 3
• Little-endian Byte 3, Byte 2, Byte 1, Byte 0
• 32 Registers with Conventions on Use

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Memory
bM
N
Registers
31

b11 b10 b9 b8
8

b7 b6 b5 b4
4
1
0
0
b3 b2 b1 b0
32 bits
32 bits
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MIPS Assembly Instructions
Instruction Example Meaning add add
s1, s2, s3 s1 s2 s3 subtract sub
s1, s2, s3 s1 s2 - s3 s1, s2, s3,
are registers. The indicates a Register in
the MIPS Assembly Language
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MIPS Assembly Instructions
Instruction Example Meaning add add
s1, s2, s3 s1 s2 s3 subtract sub
s1, s2, s3 s1 s2 - s3 s1, s2, s3,
are registers. The indicates a Register in
the MIPS Assembly Language Also s2 s3
s1
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Machine Instruction Format
R Type Instruction
Instr Format op rs rt rd shamt
funct
add R 0 reg reg reg
0 32
sub R 0 reg reg reg
0 34

bits 6 5 5 5 5
6
op opcode rd register destination
operand rs reg source 1 operand shamt
shift amount rt reg source 2 operand funct
function code variant
of operation
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Machine Instruction Format
add t0, s2, t0 where t0 is reg 8, s2 is
reg 18 t0 s2 t0
Instr Format op rs rt rd shamt
funct

add R 0 18 8 8
0 32
bits 6 5 5 5 5
6
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Machine Instruction Format
add t0, s2, t0 where t0 is reg 8, s2 is
reg 18 t0 s2 t0
Instr Format op rs rt rd shamt
funct
add R 0 18 8 8
0 32

bits 6 5 5 5 5
6
Example of Machine Language Instruction
op rs rt rd shamt
funct
0 18 8 8 0
32
000000 10010 01000 01000 00000 100000
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MIPS Assembly Instructions
Instruction Example Meaning load word
lw s1, 300 (s2) s1 Mems2300 store
word sw s1, 300 (s2) Mems2300
s1 s1, s2, s3, are registers 300 is a
constant
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Machine Instruction Format
I Type Instruction
lw s1, 300 (s2)
Instr Format op rs rt address/
immediate
lw I 35 reg reg
constant
sw I 43 reg reg
constant
bits 6 5 5 16
op opcode rs reg address operand rt reg
destination or source operand
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C statement Ai h Ai Ai h
are integers where A is an array with base in
s3 h is in s1 i is in s2
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C statement Ai h Ai, Ai
h are integers where A is an array with base in
s3 h is in s1 i is in s2
Words in an Array in memory are 4 bytes apart,
so the Address increments by 4.
Ai A3 A2 A1 A0
Base 4 i Base 12 Base 8 Base 4 Base
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C statement Ai h Ai where A
is an array with base in s3 h is in
s1 i is in s2
Compiles into assembly code denotes
comments
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C statement Ai h Ai where A
is an array with base in s3 h is in
s1 i is in s2
Compiles into assembly code denotes
comments Compute Address of Ai Base 4i
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C statement Ai h Ai where A
is an array with base in s3 h is in
s1 i is in s2
Compiles into assembly code Compute Address
of Ai Base 4i add t1, s2, s2
Temp reg t1 i i 2i add t1, t1, t1
Temp reg t1 2i 2i 4i
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C statement Ai h Ai where A
is an array with base in s3 h is in
s1 i is in s2
Compiles into assembly code Compute Address
of Ai Base 4i add t1, s2, s2
Temp reg t1 i i 2i add t1, t1, t1
Temp reg t1 2i 2i 4i add t1, t1, s3
t1 address of Ai
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C statement Ai h Ai where A
is an array with base in s3 h is in
s1 i is in s2
Compiles into assembly code Compute Address
of Ai Base 4i add t1, s2, s2
Temp reg t1 i i 2i add t1, t1, t1
Temp reg t1 2i 2i 4i add t1, t1, s3
t1 address of Ai Compute the new Ai lw
t2, 0(t1) Temp reg t2 Ai
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C statement Ai h Ai where A
is an array with base in s3 h is in
s1 i is in s2
Compiles into assembly code Compute Address
of Ai Base 4i add t1, s2, s2
Temp reg t1 i i 2i add t1, t1, t1
Temp reg t1 2i 2i 4i add t1, t1, s3
t1 address of Ai Compute the new Ai lw
t2, 0(t1) Temp reg t2 Ai add t2,
t2, s1 t2 Ai h
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C statement Ai h Ai where A
is an array with base in s3 h is in
s1 i is in s2
Compiles into assembly code Compute Address
of Ai Base 4i add t1, s2, s2
Temp reg t1 i i 2i add t1, t1, t1
Temp reg t1 2i 2i 4i add t1, t1, s3
t1 address of Ai Compute the new Ai lw
t2, 0(t1) Temp reg t2 Ai add t2,
t2, s1 t2 Ai h sw t2, 0(t1)
Store t2 into Ai
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lw t2, 0(t1) Temp reg t2 Ai add
t2, t2, s1 t2 Ai h sw t2,
0(t1) Store t2 into Ai
s117, t19, t210
Translate to MIPS Machine language using decimal
op rs rt rd
address/shamt funct
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lw t2, 0(t1) Temp reg t2 Ai add
t2, t2, s1 t2 Ai h sw t2,
0(t1) Store t2 into Ai
s117, t19, t210
Translate to MIPS Machine language using decimal
op rs rt rd
address/shamt funct 35

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lw t2, 0(t1) Temp reg t2 Ai add
t2, t2, s1 t2 Ai h sw t2,
0(t1) Store t2 into Ai
s117, t19, t210
Translate to MIPS Machine language using decimal
op rs rt rd
address/shamt funct 35 9
10 0
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lw t2, 0(t1) Temp reg t2 Ai add
t2, t2, s1 t2 Ai h sw t2,
0(t1) Store t2 into Ai
s117, t19, t210
Translate to MIPS Machine language using decimal
op rs rt rd
address/shamt funct 35 9
10 0 0 10
17 10 0
32
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lw t2, 0(t1) Temp reg t2 Ai add
t2, t2, s1 t2 Ai h sw t2,
0(t1) Store t2 into Ai
s117, t19, t210
Translate to MIPS Machine language using decimal
op rs rt rd
address/shamt funct 35 9
10 0 0 10
17 10 0
32 43 9 10
0
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lw t2, 0(t1) Temp reg t2 Ai add
t2, t2, s1 t2 Ai h sw t2,
0(t1) Store t2 into Ai
s117, t19, t210
Translate to MIPS Machine language using decimal
op rs rt rd
address/shamt funct 35 9
10 0 0 10
17 10 0
32 43 9 10
0
Translate to MIPS Machine language using binary
100011 01001 01010 0000000000000000
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lw t2, 0(t1) Temp reg t2 Ai add
t2, t2, s1 t2 Ai h sw t2,
0(t1) Store t2 into Ai
s117, t19, t210
Translate to MIPS Machine language using decimal
op rs rt rd
address/shamt funct 35 9
10 0 0 10
17 10 0
32 43 9 10
0
Translate to MIPS Machine language using binary
100011 01001 01010 0000000000000000 000000
01010 10001 01010 00000 100000
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lw t2, 0(t1) Temp reg t2 Ai add
t2, t2, s1 t2 Ai h sw t2,
0(t1) Store t2 into Ai
s117, t19, t210
Translate to MIPS Machine language using decimal
op rs rt rd
address/shamt funct 35 9
10 0 0 10
17 10 0
32 43 9 10
0
Translate to MIPS Machine language using binary
100011 01001 01010 0000000000000000 000000
01010 10001 01010 00000 100000 101011 01001
01010 0000000000000000
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Two Key Principles

• Instructions are represented the same as numbers
• Programs are stored in memory to be read or
  written just like numbers

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Two Key Principles

• Instructions are represented as numbers
• Programs are stored in memory to be read or
  written just like numbers
• This is the Stored Program Concept
• Programs can operate on other programs!