Team 1 Design Review

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Team 1 Design Review 2005/9/28

• IEE 5644 Mixed-Signal IC Design and Laboratory (I)

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Outline

1. High-Speed PAM Transceivers
2. Analog Circuit Elements for Digital Control
3. High-Speed A/D Conversion
4. High-Speed Clock/Phase Generation
5. Conclusions

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Transceiver Functions

• Encoding and Decoding.
• Waveform Shaping.
• Adaptive Equalization.
• Feed-forward Equalization (FFE).
• Decision-Feedback Equalization (DFE).
• Adaptive Timing Recovery.
• Analog-Digital Interfaces.
• DAC and ADC.
• Adaptive Gain and Offset Controls.

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PAM Transceiver Architecture
The bit-error rate (BER) is determined by the
signal-to-noise ratio (SNR) of Q(k).
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Eye Diagram
Source R. Walker, ISSCC short course, Feb. 2002.
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Conclusions

• Technology and voltage scaling will continue.
• More digital signal processing will be applied to
  future high-speed physical-layer data
  transceivers.
• Technology scaling, especially the voltage
  scaling, isnt good for analog circuits.