How to reduce the power dissipation

1
How to reduce the power dissipation?
Voltage Scaling
Switched Capacitance
Switching Activity
2
Low-Power Design Through Voltage Scaling

• Different from constant-field scaling (Full
  Scaling)

• Full Scaling power supply, as well as device
  dimension and doping density are scaled by the
  same factor.

• Voltage Scaling key device parameters and the
  load capacitances are constant.

3
Low-Power Design Through Voltage Scaling

• Influence of Voltage Scaling on Power and Delay

4
Low-Power Design Through Voltage Scaling
Can we compensate for the delay caused by
reducing the supply voltage?
?
Positive Influence

• when scaled linearly, allow the circuit to
  produce the same speed-performance at a lower
  Vdd. example

5
Low-Power Design Through Voltage Scaling
How to overcome the difficulties (leakage and
high stand-by power dissipation) associated with
the low VT circuits?
?
Solution

• Variable-Threshold CMOS Technique (VTCMOS)

• Multiple-Threshold CMOS Technique (MTCMOS)

6
Low-Power Design Through Voltage Scaling

• Variable-Threshold CMOS Technique (VTCMOS)

• VTCMOS logic circuit VSB are variable and
  generated by a variable substrate bias control
  circuit.

7
Low-Power Design Through Voltage Scaling

• Drawbacks of VTCMOS technique

• Requires twin-well or triple-well to apply
  different substrate bias voltage to different
  parts of the chip.

• Separated power pins may be required if the
  substrate bias voltage levels are not generated
  on-chip.

8
Low-Power Design Through Voltage Scaling

• Low-VT transistors design the logic gates
  where speed is essential.

• Stand-by transistors (Sleep transistors)
  isolate the logic gate in stand-by mode to
  prevent leakage dissipation.

9
Low-Power Design Through Voltage Scaling

• Drawbacks of MTCMOS circuit design technique

• Fabricate two different VT transistors on the
  same chip

• Sleep transistors increase the area and
  parasitic capacitance.

• MTCMOS is easier to implement and use compared
  to the VTCMOS.

Using system-level architectural methods
(pipelining and hardware replication ) to
maintain the system performance (throughout)
despite the voltage scaling.
Solution
10
Low-Power Design Through Voltage Scaling

• Pipelining Technique

• Single Stage Structure

11
Low-Power Design Through Voltage Scaling

• N-Stage Pipeline Structure

12
Low-Power Design Through Voltage Scaling
Theory

• Then, the logic blocks between two successive
  registers can operate N-times slower.

• This means the power supply voltage can be
  reduced to a value of VDD.new to effectively to
  slow down the circuit .

• Drawback of Pipeline Technique

• N-1 register arrays are introduced, area
  increase.

• Increases the latency from one to N clock
  cycles.

13
Low-Power Design Through Voltage Scaling

• Parallel Processing Approach (Hardware
  Replication)

14
Low-Power Design Through Voltage Scaling
Theory

• Time allowed to compute the function for each
  input vector is increased by a factor of N.

• This means the power supply voltage can be
  reduced to a value of VDD.new to effectively slow
  down the circuit .

• Drawback of Hardware Replication

• input/output routing capacitance

• increased area and latency

15
Estimation and Optimization of Switching
Activity

• The Concept of Switching Activity

aT (switching activity factor) effective number
of power-consuming voltage transition experienced
by the output capacitance per clock cycle.
Depends on the circuit topology, logic style, and
input signal statistics.
Solution
Introduce two signal probabilities

• P0 probability of having a logic 0 at the
  output.

• P1probability of having a logic 1 at the
  output. (P11-P0)

16
Estimation and Optimization of Switching
Activity
a static CMOS NOR2
transition probability is a function of the
number of inputs.
17
Estimation and Optimization of Switching
Activity

• In Multi-Level Logic Circuits

• Distribution of input signal probabilities is
  not uniform.

• Output transition probability becomes a
  function of the input probability distributions.

• Evaluation of switching activity becomes a
  complicated problem in large circuits.

• Designer rely on CAD tools for correct
  estimation .

18
Estimation and Optimization of Switching
Activity

• Transition probability in dynamic CMOS logic
  circuit.

• Power is consumed whenever the output value
  equals 0.

• Power consumption is determined by the
  signal-value probability and not by the
  transition probability

• Signal-value probability is always larger than
  transition probability.

• power consumption of dynamic CMOS logic gates
  is typically larger than static CMOS gates under
  the same conditions.

• Reduction of Switching Activity

bubble sort Vs merge sort
19
Estimation and Optimization of Switching
Activity

• Architecture Optimization

An important measure is based on delay balancing
and the reduction of the glitches. (What is
glitch, where does it come from?)
20
Estimation and Optimization of Switching
Activity
Power dissipation in the clock distribution
network can be very significant.
Conventional approach All input bits are latched
into two N-bit registers, and then applied to the
comparator circuit. Two N-bit register arrays
dissipate power in every clock cycle.
21
Estimation and Optimization of Switching
Activity
Solution
50
22
Welcome Shaw back!
23
Low-Power Design Through Voltage Scaling
Variation of the normalized propagation delay of
a CMOS inverter, as a function of the power
supply voltage Vdd and the threshold voltage VT.
24
Low-Power Design Through Voltage Scaling
2V
Substrate Bias Control Circuit
Vin
Vout
25
Low-Power Design Through Voltage Scaling

• Active mode sleep transistors on, low VT logic
  gates operate with low switching power
  dissipation and small propagation delay.

VDD
stand-by
high- VT pMOS
CMOS Logic with low VT
high-speed operation with low power consumption

• Stand-by mode sleep transistors off, conduction
  paths for any subthreshold leakage that may
  originate from the internal low-VT circuitry
  are cut off.

stand-by
high- VT nMOS
26
Estimation and Optimization of Switching
Activity
3/4 1/4 3/16
1/4 1/4 1/16
3/4 3/4 9/16
1
0
3/4 1/4 3/16
If the two inputs are independent and uniformly
distributed, then
P03/4 P11/4
27
Estimation and Optimization of Switching
Activity
0.30
Output Transition Probability
0.25
Transition probability for XOR/XNOR gate
0.20
0.15
0.10
Transition probability for NAND/NOR gate
0.05
0.00
2
3
4
5
6
7
8
Number of Inputs
28
Glitch

• Primarily due to a mismatch or imbalance in the
  path lengths in the logic network .

• Such a mismatch results in a mismatch of signal
  timing with respect to the primary inputs.

• If all input signal of a gate change
  simultaneously, no glitch.

• When glitch happens, a node exhibit multiple
  transitions in a single clock cycle before
  settling to the correct logic level. This
  contribute to the dynamic power dissipation.