Low-Power Multipliers with Data Wordlength Reduction

1
Low-Power Multipliers withData Wordlength
Reduction

• Kyungtae Han (khan_at_mail.utexas.edu)
• Brian L. Evans (bevans_at_ece.utexas.edu)
• Earl E. Swartzlander, Jr. (eswartzla_at_aol.com)
• Dept. of Electrical and Computer EngineeringThe
  University of Texas at AustinAustin, TX 78712
  USA
• Asilomar Conference on Signals, Systems
  Computers
• November 2nd, 2005

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Outline

• Introduction
• Wordlength reduction
• Power consumption
• Analysis in switching expectation
• FPGA dynamic power estimation
• Conclusion

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Introduction

• Minimize power dissipation due to limited battery
  power and cooling system
• Multipliers often a major source of power
  consumption in typical DSP applications
• Multi-precision multipliers can select smaller
  multipliers (8, 16 or 24 bits) to reduce power
  consumption
• Wordlength reduction to select any word size
  Han, Evans, and Swartzlander 2004

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Wordlength Reduction in Multiplication
Sign bit

• Input data wordlength reduction
• Smaller bits enough to represent, e.g. p x p
  9
• Truncation
• Signed right shift
• Move toward the least significant bit (LSB)
• Signed bit extended for arithmetic right shift

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Power Reduction via Wordlength Reduction

• Power dissipation
• Switching power consumption
• Static power consumption
• Switching power consumption
• Switching activity parameter, a
• Reduce a by wordlength reduction

CL Load capacitance
Vdd Operating voltage
fclk Operating frequency
What is relationship between wordlength and
switching parameter, a, in power consumption?
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Switching Activity in Multipliers

• Logic delay and propagation cause glitches
• Proposed analytical method
• Hard to estimate glitches in closed form
• Analyze switching activity w/r to input data
  wordlength
• Does not consider multiplier architecture
• Simulation method
• Count all switching activities(transition counts
  in logic)
• Power estimation (Xilinx XPower)
• Considers multiplier architecture

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Analytical Method

• Consider stream of data for one of the
  multiplicands
• Compare two adjacent numbers in stream after
  reduction
• Expectation of bitswitching, x, withprobability
  Px
• L-bit input data
• Truncate input datato M bits (N bits
  areremoved)
• N-bit signed rightshift in L-bit input(Y is
  sign bit)

L bits
M bits
N bits
S


S


S
S

S
S

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Analytical Method
X has binomial distribution
Always L/2 (independent on M and N)
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Analytical Method
Input Switching expectation
Full length used L/2
Truncate N bits M/2
N-bit signed right shift L/2
Wordlength (L) 16
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Wallace vs. Booth Multipliers
Symmetric
Asymmetric (one operand recoded)
Tree dot diagram in 4-bit Wallace multiplier
Radix-4 multiplier based on Booths recoding (?
? a P)
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Dynamic Power Consumption for Wallace Multiplier
(1MHz)
Reduction (56)
Swapping (recode,nonrecode)
16-bit x 16-bit multiplier (Simulated on
XC3S200-5FT256 FPGA)
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Dynamic Power Consumption for Radix-4 Modified
Booth Multiplier (1MHz)
Reduction (31)
Sensitive (13)
Swapping (recode,nonrecode)
16-bit x 16-bit multiplier (Simulated on
XC3S200-5FT256 FPGA)
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Conclusion

• Truncation to 8 bits reduces est. power
  consumption by 56 in Wallace and 31 in Booth
  16-bit multipliers
• Signed right shift exhibits no est. power
  reduction in Wallace multiplier (for any shift)
  and 25 reduction in Booth multipliers (for 8-bit
  shift)
• Power consumption in tree-based multiplier
• Highly depends on input data
• Simulation of all switching activity matches
  analysis of switching activity in reduced
  multiplicands in Wallace mult.
• Operand swapping can reduce power consumption
• In Booth multiplier, non-recoded operand 13 more
  sensitive in power consumption

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Thank You!
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Backup Slides
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Dynamic Power Consumption

• 16-bit x 16-bit multiplier (Simulated on
  XC3S200-5FT256 FPGA)

31
56
Swapping
Radix-4 modified Booth multiplier (1 MHz)
Wallace multiplier (1 MHz)