8' VHDL for Sequential Circuits

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8. VHDL for Sequential Circuits

• Standard form for simple state machines
• Role of synchronization conditions
• Asynchronous resets
• Defining your own functions
• Using assertion statements
• Interpretation of synthesis report
• Registers and aggregate data structures

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Synchronization Conditions
entity sparity is port ( clk, en, x in
STD_LOGIC y out STD_LOGIC ) end
sparity architecture arch of sparityv is signal
s std_logic begin process (clk) begin if
clk'event and clk '1' then if en '0'
then s lt '0' else s lt x xor
s end if end if end process y lt
s end arch
Sensitivity list specifies signals that trigger
changes
Test for rising clock edge synchronizes actions
If signal is assigned within scope of
synchronization condition, then signal is a flip
flop output
Read Remainder of VHDL Tutorial
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Serial Comparator in VHDL
entity scompare is port ( A, B, E, Clk in
STD_LOGIC A_gt_B out STD_LOGIC) end
scompare architecture arch of scompare is signal
s1, s0 STD_LOGIC begin process(clk) begin
if clk'event and clk '1' then if E '0'
then s1 lt '0' s0 lt '0' elsif s1
'0' and s0 '0' and A '1' and B '0'
then s1 lt '1' s0 lt '0' elsif s1
'0' and s0 '0' and A '0' and B '1'
then s1 lt '0' s0 lt '1' end if
end if end process A_gt_B lt s1 end arch

• Same basic structure as serial parity circuit.
• signals for flip flops
• if defines next state logic
• no change to s1, s0 when none of specified
  conditions holds
• so, no code needed for self-loops in state
  diagram
• separate signal assignment for output

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Simpler Form of Seq. Comparator
entity seqcmpv is port ( A, B, E, Clk in
STD_LOGIC A_gt_B out STD_LOGIC) end
seqcmpv architecture arch of seqcmpv is type
state_type is (unknown, Abigger, Bbigger) signal
state state_type begin process(clk) begin if
rising_edge(clk) then if E '0'
then state lt unknown elsif state
unknown then if A '1' and B '0'
then state lt Abigger elsif A '0' and
B '1' then state lt Bbigger end
if end if end if end process A_gt_B lt
'1' when state Abigger else '0' end arch
State type with named values.
Alternate form of sync condition
Use of state names makes code easier to
understand. Synthesizer can optimize state
assignment
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Understanding Synchronization Conditions

• Signal assigned value in scope of synchronization
  condition is connected to flip flop output
• so, cannot assign to same signal outside a sync
  condition
• and cannot assign same signal a value in scope of
  sync condition involving a different clock signal
• cannot assign same signal in different processes
• and usually, cannot assign same signal on both
  rising and falling edges of same clock signal
• Changes to signals assigned within scope of sync
  condition are delayed until clock occurs
• to make signal change immediately in response to
  another signal, place signal assignment outside
  sync condition
• Be careful with mixed processes
• synchronous assignments require clock in
  sensitivity list
• asynchronous assignments require all asynchronous
  inputs

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Suggested Practice for State Machines

• Define enumerated state_type with all your state
  names example type state_type is (start, add,
  shift, wait)
• Write process to update the state on each clock
  edge. process(clk) begin if rising_edge(clk)
  then if reset 1 then -- or if EN 0
  then ... state lt initial state elsif
  then - - add next state logic here end
  if end if end process
• For async outputs, use separate combinational
  process
• for simple circuits, use stand-alone assignments
• For internal registers and synchronous outputs,
  place assignments in synchronous process
• place logically related assignments in same
  process

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Using Language Templates
Select language templates (also in Edit menu)
Menu of choices
Selected template
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Flip Flops with Async Resets

• To simplify initialization, flip flops are often
  equipped with asynchronous resets.
• asynchronous resets clear flip flop independent
  of clock
• D flip flop with asynchronous reset.

• FPGAs often have asynchronous resets built-in
• to use built-in reset, VHDL must be written
  differently
• caveat using async. reset makes design less
  portable

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Async Resets in VHDL
process responds to changes in clk and reset
initialization does not depend on clk
normal state changes only allowed when reset0
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4-Way Max Finder Design

• Design a circuit with four serial inputs and a
  serial output equal to the largest input value
  (values come in msb first). Include reset and
  make output synchronous.
• Break down into three 2-way maximum circuits.
• note that 2-way max circuit works like
  comparator, but propagates largest value rather
  than simply determining which is largest

2-way max finder (Mealy)
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4-Way Max Finder VHDL
entity max4 is port ( clk, reset in
std_logic a,b,c,d in std_logic biggest
out std_logic) end max4 architecture arch of
max4 is type stateType is (eq, lt, gt) -- states
for 2-way comparator function nextState(statesta
teType x,ystd_logic) return stateType
is begin if state eq and x gt y then return
gt elsif state eq and x lt y then return
lt else return state end if end function
nextState function maxBit(state stateType
x,y std_logic) return std_logic is begin if
state gt or (state eq and x gt y) then return
x else return y end if end function maxBit
nextState function used to define next states
for each of the 2-way max finders
maxBit function used to define outputs for each
of the 2-way max finders
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• signal s_ab, s_cd, s stateType
• signal m_ab, m_cd, m std_logic
• begin
• m_ab lt maxBit(s_ab,a,b)
• m_cd lt maxBit(s_cd,c,d)
• m lt maxBit(s,m_ab,m_cd)
• process(clk) begin
• if rising_edge(clk) then
• assert m gt a or s_ab lt or s lt
• assert m gt b or s_ab gt or s lt
• assert m gt c or s_cd lt or s gt
• assert m gt d or s_cd gt or s gt
• if reset '1' then
• s_ab lt eq s_cd lt eq s lt eq
• biggest lt '0'
• else
• s_ab lt nextState(s_ab,a,b)
• s_cd lt nextState(s_cd,c,d)
• s lt nextState(s,m_ab,m_cd)

2-way max finder outputsare combinational
function of current state and input values
assertions for debuggingviolations reported in
ModelSim command window
synchronous updatingof state signals
overall output assignedsynchronously
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Simulation Results
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Synthesis Report Extract

• 
  
• Device utilization summary
• Number of Slice Flip Flops 7 out
  of 3072 0
• Number of 4 input LUTs 9 out
  of 3072 0
• Number of IOs 7
• 
  
• TIMING REPORT
• Minimum period 3.005ns (Maximum Frequency
  332.834MHz)
• Minimum input arrival time before clock
  3.302ns
• Maximum output required time after clock
  4.575ns
• Maximum combinational path delay No path
  found
• Timing constraint Default period analysis for
  Clock 'clk'
• Clock period 3.005ns (frequency 332.834MHz)
• Total number of paths / destination ports 27 /
  10
• --------------------------------------------------
  -----------------------
• Delay 3.005ns (Levels of Logic
  2)
• Source s_cd_FFd2 (FF)
  Destination s_FFd1 (FF)
• Gate Net
• Cellin-gtout fanout Delay Delay
  Logical Name (Net Name)

flip flop and LUT usage
summaryinformation
detailed clockperiod analysis
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Data Queue

• A queue is a data structure that stores a set of
  values so they can be retrieved in the same order
  they were stored.
• operations are enqueue and dequeue
• separate dataIn, dataOut ports allow simultaneous
  enqueue dequeue
• status signals empty and full
• implement using an array of registers, pair of
  of pointers and counter

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VHDL Design

• entity queue is Port (
• clk, reset in std_logic
• enq, deq in std_logic
• dataIn in std_logic_vector(wordSize-1 downto
  0)
• dataOut out std_logic_vector(wordSize-1 downto
  0)
• empty, full out std_logic)
• end queue
• architecture Behavioral of queue is
• constant qSize integer 16
• constant lgQueueSize integer 4
• type qStoreTyp is array(0 to qSize-1)
• of std_logic_vector(wordSize-1 downto 0)
• signal qStore qStoreTyp
• signal readPntr, writePntr std_logic_vector(lgQue
  ueSize-1 downto 0)
• signal count std_logic_vector(lgQueueSize downto
  0)
• function int(d std_logic_vector) return integer
  is
• -- Convert logic vector to integer. Handy for
  array indexing.
• begin return conv_integer(unsigned(d)) end
  function int
• begin

array type declaration for storing data
pointers and count register
type conversionfunction
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• if reset '1' then
• readPntr lt (readPntr'range gt '0')
• writePntr lt (writePntr'range gt '0')
• count lt (count'range gt '0')
• else
• if enq '1' and deq '1' then
• if count 0 then
• qStore(int(writePntr)) lt dataIn
• writePntr lt writePntr '1' count lt
  count '1'
• else
• qStore(int(writePntr)) lt dataIn
• readPntr ltreadPntr '1' writePntr lt
  writePntr '1'
• endif
• elsif enq '1' and count lt qSize then
• qStore(int(writePntr)) lt dataIn
• writePntr lt writePntr '1' count lt count
  '1'
• elsif deq '1' and count gt 0 then
• readPntr lt readPntr '1' count lt count -
  '1'
• end if

synchronousassignmentsto registers
simultaneous enq, deq
defining output signals
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Simulation Results
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Priority Queue

• Priority queue stores (key, value) pairs and
  always makes value with smallest key available.
• operations reset, insert new pair, delete pair
  with smallest key
• inputs - clk, reset, insert, delete, key, value
• outputs smallValue, empty, full, busy (when
  high, new inputs ignored)
• Implement as two rows of cells.
• each row has data present bit (dp) plus (key,
  value) registers
• keys in bottom row are sorted, keys in columns
  are sorted
• occupied cells to left, occupied top cell must
  have occupied cell below it

• to insert,
• shift top to right
• top-bottom swap
• to delete
• shift bottom left
• top-bottom swap

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VHDL for Priority Queue

• package commonConstants is
• constant wordSize integer 4
• end package commonConstants
• library IEEE
• use IEEE.STD_LOGIC_1164.ALL
• use IEEE.STD_LOGIC_ARITH.ALL
• use IEEE.STD_LOGIC_UNSIGNED.ALL
• use work.commonConstants.all
• entity priQueue is
• Port ( clk, reset in std_logic
• insert, delete in std_logic
• key, value in std_logic_vector(wordSize-1
  downto 0)
• smallValue out std_logic_vector(word
  Size-1 downto 0)
• busy, empty, full out std_logic
• )
• end priQueue
• architecture arch1 of priQueue is
• constant rowSize integer 4
• type pqElement is record

record used to group related data items
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• type rowTyp is array(0 to rowSize-1) of
  pqElement
• signal top, bot rowTyp
• type state_type is (ready, inserting, deleting)
• signal state state_type
• begin
• process(clk) begin
• if rising_edge(clk) then
• if reset '1' then
• for i in 0 to rowSize-1 loop
• top(i).dp lt '0' bot(i).dp lt '0'
• end loop
• state lt ready
• elsif state ready and insert '1' then
• if top(rowSize-1).dp / '1' then
• for i in 1 to rowSize-1 loop
• top(i) lt top(i-1)
• end loop
• top(0) lt ('1',key,value)
• state lt inserting

arrays of records implement two rows
make all slots empty initially
shift top row right
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elsif state ready and delete '1'
then if bot(0).dp / '0' then for i in 0
to rowSize-2 loop bot(i) lt
bot(i1) end loop bot(rowSize-1).dp
lt '0' state lt deleting end if elsif
state inserting or state deleting
then for i in 0 to rowSize-1 loop if
top(i).dp '1' and (top(i).key lt
bot(i).key or bot(i).dp '0') then bot(i)
lt top(i) top(i) lt bot(i) end if
end loop state lt ready end if end
if end process smallValue lt bot(0).value
when bot(0).dp '1' else (smallValuerange
gt '0') empty lt not bot(0).dp full lt
top(rowSize-1).dp busy lt '1' when state /
ready else '0' end arch1
shift bottom row left
compare and swap columns
async assignments to outputs, but values only
depend on state registers (so, synchronous)
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Simulation of Priority Queue
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Things You Should Know

• Understand correspondence between VHDL and
  circuit
• Standard form for simple state machines
• using symbolic state symbols
• using separate process for asynchronous outputs
• Role of synchronization conditions
• synchronous outputs vs. asynchronous
  outputs/signals
• Use of asynchronous resets
• User-defined functions
• Use of assertions for debugging
• Interpretation of synthesis report
• do the LUT and flip flop counts meet your
  expectaion?
• is the circuit performance satisfactory
• Using registers in state machines
• understanding
• Using aggregate data structures
• arrays and records