Tang Wai Chung, Matthew

1
CEG3470
Digital Circuits (Spring 2009)
Lecture 8 CMOS Inverter VTC Delay
Courtesy slides from DIC 2/e and EE141 notes
from Prof. Jan Rabaey

• Tang Wai Chung, Matthew

2
The CMOS Inverter
VDD

• VOH VDD
• VOL GND
• Ratioless ? min. size
• High input resistance
• Low output imped. (k?)
• No static power

S
G
IDP
Wp ?Wn
D
Vin
Vout
D
Wn
IDN
G
S
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PMOS Load Lines

• For DC VTC, IDN -IDP
• Graphically, looking for intersections of NMOS
  and PMOS IV characteristics
• To put IV curses on the same plot, PMOS IV is
  flipped since VDSp VDD Vout
• Also, VGSp VDD Vin

4
CMOS Inverter Load Characteristics
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CMOS Inverter VTC
saturation
resistive/linear
6
Switching Threshold as a Function of Transistor
Ratio Derivation
We assume both transistors are in velocity
saturation
where
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Switching Threshold as a Function of Transistor
Ratio

• VM is relatively insensitive to variations in the
  device ratio
• r 3, 2.5, 2 yields VM of 1.22V and 1.18V and
  1.13V
• The changing of ratio shifts the transient region
  of the VTC (consider a signal very noisy close to
  GND)

8
Determining VIH and VIL
Simplified Approach
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Gain as a Function of VDD
Reducing VDD does not affect the gain greatly,
until some threshold.
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Impact of Sizing
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Impact of Process Variations
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Process Variations

• Not all transistors are alike
• Impacts parameters such as reliability and
  performance

Define process corners SS, FF, SF, FS
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MOS Transistor as a Switch
Discharging a capacitor
ID
C
VDD
Modeled this with
vout
R
C
vin
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MOS Transistor as a Switch

• Real transistors arent exactly resistors
• Look more like current sources in saturation
• Two questions
• Which region of IV curve determines delay?
• How can that match up with RC model?

15
Transistor Discharing a Capacitor

• When a step input

ID
C
VDD
Transistor is in (velocity) saturation during
entire transition from VDD to VDD/2
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Finding Req
Averaging the values of resistances at the
endpoints of the transition region and simplify
using Taylor series
Resistance is inversely proportional to (W/L)
ratio For VDDgtgtVT VDSAT/2, the resistance
virtually independent of supply. Once VDD reaches
VT, the resistance dramically increases.
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The Transistor as a Switch
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The Transistor as a Switch
Req (W/L1) in 0.25? m CMOS process
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Inverter Capacitances
It is already complicated for an inverter.
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Inverter Capacitance Model

• Capacitance models important for analysis and
  intuition
• But often need something simpler to work with
• Simpler model
• Lump together as effective linear capacitance to
  ground
• In most process Cg Cd 1.5 2 fFW(?m)

vin
vout
CL
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Lumping the Caps

• Gate-Drain capacitances Cgd12
• M1 and M2 cut-off or in sat. during first half of
  the transient.
• Only overlapping cap. of M1 and M2
• Due to miller effect, Cgd 2GGD0W
• Diffusion capacitances Cdb1, Cdb2
• Quite non-linear and depends heavily on the
  applied voltage.
• Wire Capacitance Cw
• Gate Capacitance of Fanout Cg3 and Cg4

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The Miller Effect

• During low-to-high or high-to-low transitions,
  Vin increases, Vout drops
• So, Cgd experiences voltage swing larger than Vin
• Which means you need to provide more charge
• Make Cgd look larger than it really is
• Known as the Miller Effect in the analog world.

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Transient Response
tp 0.69 CL (ReqnReqp)/2
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Delay as a Function of VDD
choose VDDgtgtVTn VDSATn/2, then
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Design Techniques
How can we minimize the propagation delay of a
gate?

• Reduce CL
• reudce diffusion and interconnect cap.
• Increase the W/L ratio of the transistors
• The most powerful and effective performance
  optimization tool.
• Increase VDD
• This trade-pff energy dissipation for performance.