The Processor Data Path

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The ProcessorData Path ControlChapter 5Part
4 Exception Handling

• N. Guydosh
• 3/1/04

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Introduction

• Exceptions vs. Interrupts
• Meaning of terms depends on system and
  manufacturer.
• Both terms imply events other that branches or
  jumps that change the normal flow of execution
• Typically an exception is an unexpected event
  within the processor such as overflow and an
  interrupt is from outside the processor such as
  an I/O request
• Sometimes either term is used for both conditions
• MIP convention (used here) An exception is
  refers to any unexpected change in control flow
  without distinguishing whether the cause is
  internal or external.
• Requires immediate response from the processor -
  a hardware branch or trap to an exception
  handling routine
• Detecting and responding to exceptions may be on
  the performance critical path and could impact
  clock cycle time and performance.
• Two type of exceptions will be considered here
• Undefined instructions
• Arithmetic overflow

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Exception Handling Approach

• Basic exception handling approach
• Save the address of the offending instruction in
  an Exception Program Counter (EPC) and transfer
  control to the exception handling entry point in
  the OS.
• Two methods handling exceptions
• Single entry point for all exceptions (above) and
  put the cause of the problem in a status
  register (cause register). Used by MIPS.
• Vectored interrupts the address to which control
  is transferred is a function of the cause of the
  exception. This is the approach used in the PC
  (Intel). Uses the interrupt vector table at the
  start of ram to branch to the correct interrupt
  handling routine (DOS or bios). No need for
  cause register.

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Implementation

• Add two new 32 bit registers EPC and Cause
  Register
• For our example the low bit of cause will have a
  1 or 0 indicating undefined instruction or
  overflow.
• EPC Will be the address of the offending
  instruction. Note that the current PC will not
  be correct for the EPC because it was incremented
  early in the cycle. 4 must be subtracted from
  it, but this is ease because 4 is already an
  input to ALU and exception state simply has to
  assert ALUOP 01 (subtract). See final state
  diagram.
• Additions to the data path
• Control line EPCWrite - Write (the address of
  the offending inst) to the EPC when asserted
• Control line CauseWrite - Write(the cause code)
  to the cause register
• Modify control lines PCSource to use the
  previously unused value of 11 This will select
  a constant value for the PC (0xC0000000) which is
  the single entry point address of the exception
  handler.
• Add an extension to the state diagram (FSM) to
  handle exceptions
• Bad opcode will branch off state 1 (instruction
  decode)
• Overflow will branch off state 7 (last state of R
  - type after arithmetic is done

5
Mult-cycle Data Path With Exception Handling
Support
Cause and EPC registers added and expanded MUX
for PC selection along with associated control
lines.
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Mult-Cycle FSM With Exception Handling Support
States 10 and 11 added note ALUOp is set to 01
(subtract) to correct PC before writing to EPC.
Ignore the small