Operational Machines: ASCI White

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Operational Machines ASCI White

• Presented to SOS7
• Mark Seager
• seager_at_llnl.gov
• 925-423-3141
• ICCD ADH for Advanced Technology
• Lawrence Livermore National Laboratory

This work was performed under the auspices of the
U.S. Department of Energy by the University of
California, Lawrence Livermore National
Laboratory under Contract No. W-7405-Eng-48.
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Q1 Is your machine living up to the performance
expectations? If yes, how? If not, what is the
root cause?

• ASCI White is providing robust cycles to the
  tri-laboratory community
• Application performance relative to peak is less
  than expected
• FMA 5-16 of floating point arithmetic
  instructions issued
• Some users sacrifice (turn off) compiler
  optimization to have strict reproducibility
• Modern coding techniques lead to poor memory
  bandwidth utilization
• Low cache-line payload utilization
• OOP and non-uniform grids ? several memory
  references per floating point operation

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Q2 What is the MTBI?
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What are the topmost reasons for HW interrupts?
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What are the topmost reasons for SW interrupts?
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What is the average utilization rate?
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Q3 What is the primary complaint, if any, from
the users?

• Not enough time on the machine
• Users want more access
• Scalability of MPI
• MPI_ALLREDUCE
• MPI_BARRIER
• Extremely long job startup