EMC Guidelines

1
EMC Guidelines
2
Summary

• Golden Rules for low emission
• Power supply routing strategy
• Decoupling capacitance
• Reduction of current peak
• 2. Golden Rules for low susceptibility
• Decoupling capacitance
• Isolation of Noisy blocks

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Golden Rules for Low Emission
Rule 1 Power supply routing strategy

1. Use shortest interconnection length for supply
2. Place enough supply pairs
3. Place supply pairs close to noisy blocks
4. Place VSS and VDD pins as close as possible

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Golden Rules for Low Emission
Rule 1 Power supply routing strategy
A) Use shortest interconnection to reduce the
serial inductance

• Inductance is a major source of resonance
• Each conductor acts as an inductance
• Ground plane modifies inductance value (worst
  case is far from ground)

Reducing inductance decreases SSN !!
Lead L0.6nH/mm
Bonding L1nH/mm
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Golden Rules for Low Emission
Rule 1 Power supply routing strategy
A) Use shortest interconnection to reduce the
serial inductance
Leadframe package L up to 10nH
Die of the IC
bonding
Long leads
Far from ground
PCB
Short leads
Flip chip package L up to 3nH
balls
Die of the IC
Close from ground
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Golden Rules for Low Emission
Rule 1 Power supply routing strategy
B) Place enough supply pairs Use One pair
(VDD/VSS) for 10 IOs
9 I/O ports
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Golden Rules for Low Emission
Rule 1 Power supply routing strategy
C) Place supply pairs close to noisy blocks
Memory
PLL
Digital core
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Golden Rules for Low Emission
Rule 1 Power supply routing strategy
D) Place VSS and VDD pins as close as possible

• to increase decoupling capacitance that reduces
  fluctuations
• to reduce current loops that provoke magnetic
  field

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Golden Rules for Low Emission
Rule 1 Power supply routing strategy
Case study 1
Case study 1 Infineon Tricore Worst case not
enough supply pairs, bad distribution
dissymmetry
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Golden Rules for Low Emission
Rule 1 Power supply routing strategy
Case study 2
2 FPGA , same power supply, same IO drive, same
characteristics Supply strategy very different !

• More Supply pairs for IOs
• Better distribution

courtesy of Dr. Howard Johnson, "BGA Crosstalk",
www.sigcon.com
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Golden Rules for Low Emission
Rule 1 Power supply routing strategy
Case 1 low emission due to a large number of
supply pairs well distributed
Case 2 higher emission level (5 times higher)
courtesy of Dr. Howard Johnson, "BGA Crosstalk",
www.sigcon.com
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Golden Rules for Low Emission
Rule 2 Add decoupling capacitance
to keep the current flow internal to reduce the
supply voltage swing
Customers specification
Parasitic emission (dBµV)
80
No decoupling
Volt
70
60
50
time
40
30
20
Internal voltage drop
10
0
-10
1
10
100
1000
Frequency (MHz)
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Golden Rules for Low Emission
Rule 2 Add decoupling capacitance
Example effect of on-chip decoupling capacitance
on radiated emission
On-chip decoupling
No decoupling

• 1nF added to a normal core
• More than 15dB noise reduction

Do not place too large capacitance ? space
consuming and inefficient
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Golden Rules for Low Emission
Rule 2 Add decoupling capacitance
On chip decoupling capacitance versus technology
and complexity
Intrinsic on-chip supply capacitance
65nm
100nF
90nm
0.18µm
10nF
0.35µm
1.0nF
100pF
Devices on chip
10pF
100K
1M
10M
100M
1G
Example in 90nm technology, for a 100 Million
devices on chip the intrinsic capacitance is 10nF
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Golden Rules for Low Emission
Rule 3 Reduce current peak

• Reduce supply voltage
• Optimize IC activity, use distributed clock
  buffers
• Reduce di/dt of I/O by controlling slew rate and
  drive (depending on load)
• Add controlled jitter on clock signal to spread
  noise spectrum
• Asynchronous design spreads noise on all spectrum
  (10 dBµV reduction)

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Golden Rules for Low susceptibility
Rule 1 Decoupling capacitance is also good for
immunity
Immunity level (dBm)

• DPI aggression of a digital core
• Reuse of low emission design rules for
  susceptibility
• Efficiency of on-chip decoupling combined with
  resistive supply path

Decoupling capacitance
Substrate isolation
No rules to reduce susceptibility
Work done at Eseo France (Ali ALAELDINE)
Frequency
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Golden Rules for Low susceptibility
Rule 2 Isolate Noisy blocks

• Why
• To reduce the propagation of switching noise
  inside the chip
• To reduce the disturbance of sensitive blocks by
  noisy blocks (auto-susceptibility)
• How
• by separate voltage supply
• by substrate isolation
• by increasing separation between sensitive blocks

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Golden Rules for Low susceptibility
Rule 2 Isolate Noisy blocks
Identification of noisy and sensitive IOs
I/O type Emission sensitivity
Fast digital Output -
Output PA --
Power switch --
Fast digital input -
Power supply for digital -
Reset -
Antennas input --
Analog input --
Power supply for anaolg --
Oscillator input --
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Golden Rules for Low susceptibility
Rule 3 Reduce desynchronizations issues

• Synchronous design are sensitive to propagation
  delay variations due to jitter (dynamic errors)
• Improve delay margin to reduce desynchronization
  failures in synchronous design
• Asynchronous logic design is less sensitive to
  delay compared to synchronous design

15 dB
Work done at INSA Toulouse/TIMA Grenoble
(Fraiddy BOUESSE)
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Case Study

• Your definitive solution for embedded electronics
• 16 bit MPU with 16 MHz external quartz,
• on-chip PLL providing internal 133MHz operating
  clock.
• 128Kb RAM, 3 general purpose ports (A,B,C, 8bits)
• 4 analog inputs 12 bits, CAN interface

StarChip 1
Susceptible
Emission
SIGNAL Description
VDD Positive supply
VSS Logic Ground
VDD_OSC Oscillator supply
VSS_OSC Oscillator ground
PA0..7 Data port A (programmable drive)
PB0..7 Data port B (programmable drive)
PC0..7 Data port C (programmable drive) external 66MHz data/address
ADC In 0..3 4 analog inputs (12 bit resolution)
CAN Tx CAN interface (high power, 1MHz)
CAN Rx CAN interface (high power, 1MHz)
XTL_1, XTL_2 Quartz oscillator 16MHz
CAPA PLL external capacitance
RESET Reset microcontroller
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Case Study
StarChip 1 initial floorplan
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Case Study
StarChip 1 your floorplan
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A case study
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Companion Tools
IC-EMC A demonstrator for predicting EMC of
integrated circuits
http//www.ic-emc.org
IC-EMC v1.5
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Case study reduction of emission
Case study ICEM model of the core of a 16 bit
microcontroller
Characteristics
Technology 0.25 µm
Number of gates 100 Kgates
Activity 10
Clock frequency 10 MHz
Package type QFP 144
Supply pairs 1
ICEM model expert
Resulting ICEM model
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Case study reduction of emission
Effect of the reduction of package inductance
A second supply pair is added to divide by 2 the
overall supply inductance

• Effect on external conducted noise
• Frequency shift of spectrum emission
• No significant reduction

L5 nH
L10 nH
L10 nH

• Effect on internal voltage drop
• Reduction of emission level in low frequency
• 15 dB reduction on fundamental harmonic

L5 nH
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Case study reduction of emission
Effect of on-chip decoupling capacitor
The on-chip decoupling is increased, from 1 nF to
5 nF

• Effect on external conducted noise
• Significant reduction above 20 Mhz (above primary
  resonance frequency of the decoupling capacitor)

C1 nF
C5 nF
C1 nF
C5 nF

• Effect on internal voltage drop
• Significant reduction above 20 Mhz (above primary
  resonance frequency of the decoupling capacitor)