FSMs in Verilog and other random things

1
FSMs in Verilog and other random things

• 9/27/02

2
FSM structure
Inputs
Next State Logic
Output Logic
STATE
Outputs
CLK
3
change1
Red
Yellow
Green
change1
change1
4
module trafficLightFSM(clk,reset,change,red,yellow
,green) input clk,reset,change output
red,yellow,green reg red,yellow,green reg
10 curState,nextState parameter showRed
2b00, showYellow 2b01 parameter showGreen
2b10
// state register always _at_(posedge clk) if
(reset1b1) curState lt 2b0 else curState lt
nextState
5
// next state logic // dependent only on the
current state and input always _at_(curState or
change) begin nextState showRed // default
state case (curState) showRed if (change)
nextStateshowGreen showYellow if (change)
nextStateshowRed else nextStateshowYellow
showGreen if (change) nextStateshowYellow
else nextStateshowGreen endcase end
6

• // Output Logic dependent ONLY on state
• always _at_(curState) begin
• // ALWAYS put default output values
• red1b0 green1b0 yellow1b0
• case (curState)
• showRed red1b1
• showYellow yellow1b1
• showGreen green1b1
• endcase
• end
• endmodule

7
Edge Detector
OUT
IN
c
a
b
clk
in
a
b
c
out
8
Non-blocking

• always _at_(posedge clk)
• begin
• E lt A
• C lt E
• end

E
A
C
9
Blocking

• always _at_(posedge clk)
• begin
• E A
• C E
• end

E
A
C