ECE 994

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ECE 994

• 01 12725 Adv Top/
• System on a Chip 3.0 T R 1110-1230 PM
• KING S320
• A Rucinski

2
ECE 994Programmable System-on-a-Chip (PSoC)
DesignProf. Andrzej Rucinski

• Todays guest host -- Ted Kochanski
• Dept of ECE UNH
• tpz_at_unh.edu
• tedpk_at_alum.mit.edu
• 781 861 6167

3
ECE-994 Calendar

• Aug. 29 1100 am S320 Kingsbury - Ted Kochanski
• Course Organization
• Current schedule Aug 31 1100 AM
• Prof. Rucinski suggests to re-schedule to 1
  session per week
• Preference for Thursday 1130 230 PM working
  lunch
•  Sept. 7 1130 am Ted Kochanski
• Project Description
• September 14 Andrzej Rucinski
• Introduction to Programmable Systems on a Chip

4
ECE994 Programmable System-on-a-Chip (PSoC) Design

• the IEEE is exploring new areas where we can
  further assist technical professionals to
  distinguish themselves in the globally
  competitive environment. One possibility is to
  develop TECHNICAL CURRENCY PROGRAMS
• Michael R. Lightner, IEEE President, Enabling
  Members to Compete Globally, IEEE Spectrum,
  March 2006

5
ECE994 PSoC Design

• The UNH and the University of Tennessee is
  offering this course in PSoC systems engineering
  in response to the challenges of flat world,
  globalization and outsourcing facing todays
  engineering profession and the demand for systems
  engineers by major United States employers.
• The goal of the experimental course is to prepare
  students to design and implement microelectronic
  systems using best practices of the US high
  tech industry today

6
ECE 994 Catalog Description

• Overview of Field Programmable Gate Arrays
  (FPGAs), Application Specific Integrated Circuits
  (ASICs), System-on-a-Chip (SoC), and Programmable
  SoC (PSoC)
• Networks and constellations
• Intellectual Property (IP) module design in VHDL
  and synthesis oriented implementation using
  multiple technologies (Altera and Xilinx)
• Integration of IP modules and sensor devices with
  an existing SoC
• Collaborative and distant learning techniques for
  distributed team management and design
• In-situ and remote development scenarios.
• 4credits Lab Xilinx Development Kit

7
ECE994 PSoC Design

• Course Coordinator Dr. Andrzej Rucinski
• University of New Hampshire Kingsbury W321,
• andrzej.rucinski_at_unh.edu
• 603 862 1381
• Instructors
• Dr. Don Bouldin, University of Tennessee
  Programmable System-on-a-Chip (PSoC)
• Dr. Kent Chamberlin, University of New Hampshire
  Global Education Microelectronic Systems
  network (GEMS)
• Dr. Ted Kochanski, University of New Hampshire
  --Global Ambient Intelligence Network (GAIN)

8
ECE 994 PSoC DesignExtras

• 2007 IEEE International Conference on
  Microelectronic Systems Education
  (http//www.mseconference.org/) and the Special
  Issue of IEEE Transactions on Education
• IEEE Computer Society
• IEEE Critical Infrastructure Dependability
  Initiative and the IEEE Central New England
  Council
• Mentor Graphics High Education Program
  (http//www.mentor.com/company/higher_ed/index.cfm
  )
• XILINX University Program (http//www.xilinx.com/u
  niv/index.htm)
• Textbook Clive Max Maxfield, The Design
  Warriors Guide to FPGAs Devices Tools, and
  Flows, Elsevier 2004
• First Organizational Meeting Tuesday, August 29,
  2006, 1100 am, Kinsgbury S320

9
Xilinx Virtex II Development Board for XUP
10
MicroBlaze-based Embedded Design
I-Cache BRAM
Local Memory Bus
Flexible Soft IP
BRAM
Configurable Sizes
D-Cache BRAM
Off-Chip Memory
FLASH/SRAM
11
PowerPC-based Embedded Design
Full system customization to meet performance,
functionality, and cost goals
12
Clive Max MaxfieldThe Design Warriors Guide
to FPGAs Devices Tools, and FlowsElsevier 2004
Price 67.93Format  Adobe Reader PDF
www.ebookmall.com/ebook/149053-ebook.htm
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Maxs perspectiveFundamental Concepts

• What are FPGAs and why are they of interest?
• Underlying technologies, such as
• Antifuses
• flash memory
• and SRAM cells
• Alternative architectures and concepts
• Different programming techniques
• Who are the various players in the FPGA space?

14
More MaxAn in-depth look at

• FPGA versus ASIC design styles see ECE 715
• Schematic-based design flows (yes, they are still
  used to support legacy designs)
• HDL-based design flows
• Silicon virtual prototyping for FPGAs
• C/C-based design flows
• DSP-based design flows
• Embedded processor-based design flows
• Modular and incremental design
• High-speed design
• Migrating ASIC designs to FPGAs, and vice versa

15
Maxs Peripheral Topics

• Choosing the right device
• Gigabit serial interfaces
• Reconfigurable computing
• Field programmable node arrays (FPNAs)
• Independent design tools
• Creating a design flow based on opensource tools

16
Ted onEvolution of Technology, Industry,
Engineering Employmentpresented at Gdansk
University of Technology, May 2005

• Ted Kochanski
• Dept of ECE UNH
• tedpk_at_alum.mit.edu
• tpz_at_unh.edu
• 781 861 6167

17
Evolution of Technology, Industry, Engineering
Employment
18
Evolution of Technology, Industry, Engineering
Employment
19
Evolution of Technology, Industry, Engineering
Employment
20
Another Perspective on Technical Evolution

• Gordon Moores observations
• Exponential Lithographic feature shrink
• Increasing area of semiconductor wafers and chips
• Decreasing thickness of oxides
• Decreasing operating voltages
• Increasing speed of operations
• Exponential increase in the of transistors and
  complexity of design
• Exponential increase in the cost of fabrication

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Traditional VLSI Design Flow
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Why PSOC

• Obvious advantage simpler and quicker design
  . most of the design is already done
• Cell arrays, mask programmable gate arrays
• Field Programmable devices PLD, FPGA
• Less obvious easier re-use, modularity
• Still less obvious easier collaborative and
  remote design
• May be cheaper
• More flexible
• Easy to fix
• Reconfigurable on the fly

31
Why Not PSOC until recently

• Not enough capabilities
• Clock speed
• Gates
• I/O
• Memory
• Less developed tools
• Too Expensive
• Too hard to test and verify
• Now on-chip monitoring

32
Cost of Masks
33
Cost of Fabs
34
Trade-offs

• Mask sets now define costs of full custom
• Need very large volume and no changes to justify
• Design personnel and tools as well as time to
  market now define the bounds of ASICs
• Cost of raw devices now define the bounds of FPGA
  and PSOC

35
Systems Implementation
36
Integration in System Design
Integration of Functions
Time
37
Still Another Perspective

• Suppose you could build an Intelligent Sensor
  Network
• What could you do with it?
• How would you do it?

38
Generic Sensor System
I. Introduction and definitions
Location, dL Full Scale Range Sensitivity Accuracy
Precision Noise
Sensing Transducer
Observer, User or Actuator
Desired Measurement Model
Physical Variable
39
What is a Sensor Network
I. Introduction and definitions
Signal Conditioning
Sensor
Control
Processing
Comm
Storage
Comm Link
User Interface
User
Model
40
What do you do with it
I. Introduction and definitions

• Observe
• Measure
• Control
• Characterize
• Understand
• Synthetic Reality

41
Some Examples of Applications of Sensor Networks
I. Introduction and definitions

• Military reconnaissance, radar-based air-defense 
  
• Chemical, Biological, Radiological, Nuclear, and
  Explosive (CBRNE) detection
• Environmental monitoring
• Traffic monitoring 
• Security cameras monitoring shopping malls,
  parking garages, and other public facilities
• Free spots in a parking garage

42
Intelligent Sensor Networks

• I. Introduction and definitions
• II. Key pieces of the core technology
• III. 1950s Technology how it began
• IV. Current off the shelf technology
• V. Applications
• VI. Areas that still need lots of work and the
  future
• VII. Conclude

43
Intelligent Sensor Networks
II. Key pieces of the core technology

• Self/Reconfigurable Network Interconnections
• Self-organizing Network
• Reconfigurable, Collaborative Processing
• The Network as Computer
• Queryable Storage Network
• The Network as Database

44
Intelligent Sensor Network Functions
II. Key pieces of the core technology

• Determine the local value of some parameter
• Multiple types of sensors with different sampling
  rates
• Detect events of interest and estimate
  parameters  
• traffic entering intersection / speed
• Classify a detected object  
• Is a vehicle a car, a mini-van, a light truck, a
  bus, etc.
• Track an object
• Follow an emergency vehicle en route to a fire

45
Network Self-organization Essential
II. Key pieces of the core technology

• Given
• The large number of nodes
• Potential hostile locations
• Nodes failure
• Individual nodes may become disconnected
• New nodes may join the network
• To maintain high degree of overall connectivity
  manual configuration is not feasible
• Must be able to periodically reconfigure itself

46
Collaborative signal processing  
II. Key pieces of the core technology

•  Improve performance in the detection/estimation
  of events of interest
• Useful to fuse data from multiple sensors
• Requires transmission of both data and control
  messages
• May put constraints on the network architecture

47
Querying Ability  
II. Key pieces of the core technology

• May want to query
• individual nodes
• group of nodes in a region
• Data fusion drives required network Bandwidth
• Network connectivity and bandwidth may limit
  amount of the data transmitted across the network
• Local sink nodes will collect the data from a
  given area and can create summary messages
• Direct query to the regional sink node
• Possible penalty is increased response time

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Ambient User Interface
II. Key pieces of the core technology
49
Whirlwind
III. 1950s digital sensor networking
50
Whirlwind (1950)
III. Project Lincoln 1950s digital sensor
networking

• Original design
• 256 16 bit words Electrostatic tube memory
  (Williams-Kilburn tubes)
• 8,500 microseconds (ms) access for drum memory
• 20 KIPS with
• Addition time 49 ms
• multiplication time 61 ms
• Redesign
• Magnetic-Core memory (Forester)
• 40 KIPS
• Addition time of 8 ms
• Multiplication time 25.5 ms, division time of
  57ms
• 8 ms memory access time

51
SAGE
III. Project Lincoln 1950s digital sensor
networking
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Sit! Rest!
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Part 2 Rest stop
54
ECE 994

• 01 12725 Adv Top/
• System on a Chip 3.0 T R 1110-1230 PM
• KING S320
• A Rucinski

55
ECE 994Programmable System-on-a-Chip (PSoC)
DesignProf. Andrzej Rucinski

• Todays guest host -- Ted Kochanski
• Dept of ECE UNH
• tpz_at_unh.edu
• tedpk_at_alum.mit.edu
• 781 861 6167

56
ECE-994 Calendar

• Aug. 29 1100 am S320 Kingsbury - Ted Kochanski
• Course Organization
• Current schedule Aug 31 1100 AM
• Prof. Rucinski suggests to re-schedule to 1
  session per week
• Preference for Thursday 1130 230 PM working
  lunch
•  Sept. 7 1130 am Ted Kochanski
• Project Description
• September 14 Andrzej Rucinski
• Introduction to Programmable Systems on a Chip

57
ECE 994 PSoC Introduction to the XiLinx FPGA
Development Environment

• Websites
• http//www.xilinx.com/xlnx/xweb/xil_publications_i
  ndex.jsp?categoryUserGuidesBV_SessionID_at__at__at__at_011
  5701314.1157625249_at__at__at__at_BV_EngineIDccciaddijlijgfe
  cefeceihdffhdfjf.0
• http//www.digilentinc.com/Products/Detail.cfm?Nav
  1ProductsNav2ProgrammableProdXUPV2P

58
Virtex-II Pro Development SystemCurriculum on a
Chip
59
Hardware Reference Manual
60
Power Supply Issues

• XUPV2P Features
• Virtex-2 Pro XC2VP30 FPGA with
• 30,816 Logic Cells
• 136 18-bit multipliers,
• 2,448Kb of block RAM,
• 2 PowerPC Processors
• DDR SDRAM DIMM that can accept up to 2Gbytes of
  RAM
• 10/100 Ethernet port
• USB2 port
• Compact Flash card slot
• XSGA Video port
• Audio Codec
• SATA, and PS/2, RS-232 ports
• High and Low Speed expansion connectors,
• large collection of available expansion boards

61
XUPV2P

• Can function as a
• digital design trainer,
• microprocessor development system,
• host for embedded processor cores and complex
  digital systems.
• Expansion connectors can accommodate
  special-purpose circuits and systems for years to
  come
• Supported by world-class design tools, including
• ISE Foundation,
• Chipscope-Pro,
• Embedded Developer's Kit (EDK),
• and System Generator (WebPack cannot be used).
• Applications that include an embedded processor
  require EDK, and those that do not include a
  processor can use ISE

62
XUPV2P Block Diagram
63
XUPV2P BIST
64
Demonstration Reference Designs 

• XUPV2P Demonstration Design uses the AC 97 audio
  codec as the audio A/D and D/A to the Xilinx
  XC2VP30 FPGA, for capturing audio to be filtered
  and played back to the user's speakers.
• Video Decoder using VDEC-1 uses an Analog Devices
  ADV7183B to sample the incoming analog video and
  convert it to digital values according to the
  video standards ITU-R.656 and ITU-R BT.601.
• Slide Show using 256 MB DDR Memory reads binary
  graphic data (.bmp) stored on a compact flash and
  presents it on an external display monitor.
• Ethernet MAC OneWire implements a web server
  running on the XUP-V2Pro Development System, with
  a OneWire core. The WEB server will display the
  user DIP switches and control the LEDs from your
  browser.
• OneWire implements a a OneWire core. The core
  reads the silicon serial number and displays it
  on the terminal window through a UART.  
• PS2 implements a core which reads in the
  characters typed in on a keyboard connected to
  either of the two PS2 ports and displays it on
  the terminal window through a UART.
• Edge Detection shows how a 2-D Image filter can
  be efficiently realized using n-tap MAC FIR
  Filters.

65
XUPV2P Demonstration Design

• Uses the AC 97 audio codec as the audio A/D and
  D/A to the Xilinx XC2VP30 FPGA, for capturing
  audio to be filtered and played back to the
  user's speakers.
• The filtered or unfiltered digital audio data is
  presented to a 64 point FFT to convert the time
  domain audio, to frequency domain spectral
  information.
• The output of the FFT is sampled and displayed
  graphically using character mapped graphics to an
  800 X 600 pixel VGA resolution display using
  Fairchild FMS3818 D/A to take the digital data
  from the FPGA to the SVGA analog output. 

66
Video Decoder using VDEC-1

• Uses an Analog Devices ADV7183B to sample the
  incoming analog video and convert it to digital
  values according to the video standards ITU-R.656
  and ITU-R BT.601.
• In this example design, the video is then further
  converted to be displayed on a standard VGA
  display as progressive video output on the XUP
  boards SVGA port.

67
Slide Show using 256 MB DDR Memory

• Reads binary graphic data (.bmp) stored on a
  compact flash and presents it on an external
  display monitor.
• It uses the System Ace controller to read data
  from compact flash into memory, on 2 MB
  boundaries.
• The memory controller is setup for a 256 MB Dimm.
  
• By moving the VGA display pointer, the data is
  presented like a slide slow through the XSGA port
  from the FPGA to the SVGA analog output.

68
Ethernet MAC OneWire

• Implements a web server running on the XUP-V2Pro
  Development System, with a OneWire core.
• The WEB server will display the user DIP switches
  and control the LEDs from your browser.
• The core uses the silicon serial number as an
  Ethernet MAC address, although the serial number
  is unique for all the boards, it is not a
  registered MAC address. 
• OneWire implements a a OneWire core.
• The core reads the silicon serial number and
  displays it on the terminal window through a
  UART.  

69
PS2 Demonstration Reference Design 

• Implements a core which reads in the characters
  typed in on a keyboard connected to either of the
  two PS2 ports and displays it on the terminal
  window through a UART.

70
Edge Detection

• Shows how a 2-D Image filter can be efficiently
  realized using n-tap MAC FIR Filters.
• The filters used in the '5x5 Filter' subsystem
  are from the Custom FIR library provided as a
  System Generator For DSP demo.
• The sysgenConv5x5_hw_in_lup.mdl example uses the
  XUP-V2P Development System as a hardware
  accelerator to decrease simulation time.

71
Power PC 405 Block
72
Valuable Reference Docs
73
Virtex-II Platform FPGA User Guide

• Chapter 1, The Virtex-II Pro / Virtex-II Pro X
  FPGAFamily
• Chapter 2, Timing Models
• Chapter 3, Design Considerations
• Chapter 4, Configuration
• Chapter 5, PCB Design Considerations
• Appendix A, BitGen and PROMGen Switches and
  Options
• Appendix B, Platform Flash Family PROMs
• Appendix C, Choosing the Battery for VBATT

74
PowerPC Processor Reference Guide

• Introduction to the PPC405, provides a general
  understanding of the PPC405 as an implementation
  of the PowerPC embedded-environment architecture.
• Operational Concepts, introduces the processor
  operating modes, execution model,
  synchronization, operand conventions, and
  instruction conventions.
• User Programming Model, describes the registers
  and instructions available to application
  software.
• PPC405 Privileged-Mode Programming Model,
  introduces the registers and instructions
  available to system software.
• Memory-System Management, describes the operation
  of the memory system, including caches. Real-mode
  storage control is also described in this
  chapter.
• Virtual-Memory Management, describes
  virtual-to-physical address translation as
  supported by the PPC405. Virtual-mode storage
  control is also described in this chapter.

75
PowerPC Processor Reference Guide

• Exceptions and Interrupts, provides details of
  all exceptions recognized by the PPC405 and how
  software can use the interrupt mechanism to
  handle exceptions.
• Timer Resources, describes the timer registers
  and timer-interrupt controls available in the
  PPC405.
• Debugging, describes the debug resources
  available to software and hardware debuggers.
• Reset and Initialization, describes the state of
  the PPC405 following reset and the requirements
  for initializing the processor.
• Instruction Set, provides a detailed description
  of each instruction supported by the PPC405.

76
PowerPC Processor Reference Guide

• Register Summary, is a reference of all registers
  supported by the PPC405.
• Instruction Summary, lists all instructions
  sorted by mnemonic, opcode, function, and form.
  Each entry for an instruction shows its complete
  encoding. General instruction-set information is
  also provided.
• Simplified Mnemonics, lists the simplified
  mnemonics recognized by many PowerPC assemblers.
  These mnemonics provide a shorthand means of
  specifying frequently-used instruction encodings
  and can greatly improve assembler code
  readability.
• Programming Considerations, provides information
  on improving performance of software written for
  the PPC405.
• PowerPC 6xx/7xx Compatibility, describes the
  programming model differences between the PPC405
  and PowerPC 6xx and 7xx series processors.
• PowerPC Book-E Compatibility, describes the
  programming model differences between the PPC405
  and PowerPC Book-E processors.

77
PowerPC 405 Processor Block Reference
GuideEmbedded Development Kit

• Chapter 1, Introduction to the PowerPC 405
  Processor, provides an overview of the PowerPC
  embedded-environment architecture and the
  features supported by the PowerPC 405 processor
  block.
• Chapter 2, Input/Output Interfaces, describes
  the interface signals into and out of the PowerPC
  405 processor block. Where appropriate, timing
  diagrams are provided to assist in understanding
  the functional relationship between multiple
  signals.
• Chapter 3, PowerPC 405 OCM Controller,
  describes the features, interface signals, timing
  specifications, and programming model for the
  PowerPC 405 on-chip memory (OCM) controller. The
  OCM controller serves as a dedicated interface
  between the block RAMs in the FPGA and OCM
  signals available on the embedded PowerPC 405
  core.
• Chapter 4, PowerPC 405 APU Controller,
  describes the Auxiliary Processor Unit
  controller, which allows the designer to extend
  the native PowerPC 405 instruction set with
  custom instructions that are executed by an FPGA
  Fabric Co-processor Module (FCM). The APU
  controller is available only for Virtex-4 family
  devices.

78
PowerPC 405 Processor Block Reference
GuideEmbedded Development Kit

• Appendix A, RISCWatch and RISCTrace Interfaces,
  describes the interface requirements between the
  PowerPC 405 processor block and the RISCWatch and
  RISCTrace tools.
• Appendix B, Signal Summary, lists all PowerPC
  405 interface signals in alphabetical order.
• Appendix C, Processor Block Timing Model,
  explains all of the timing parameters associated
  with the IBM PPC405 Processor Block.

79
Current Technology Trends and COTS
IV. Current technology trends and COTS

• Network Architectures
• Processor Scalability
• COTS Wireless Sensor Elements

80
Network Features
IV. Current technology trends and COTS
Network Architecture for Ambient Intelligence

• Scalability with large number of (mostly
  stationary) sensors
• Networks of 10,000 or even 100,000 nodes
• Stationary -- except for
• Ocean surface
• Mobile robotic sensors
• Network self-organization
• Collaborative signal processing
• Querying ability
• Low energy use

81
Network Architecture
IV. Current technology trends and COTS
Network Architecture for Ambient Intelligence

• Self/Reconfigurable Network Interconnections
• Self-organizing Network
• Reconfigurable, Collaborative Processing Network
• The Network as Computer
• Queryable Storage Network
• The Network as Database

82
NIST on Sensor Network Architecture
IV. Current technology trends and COTS
Network Architecture for Ambient Intelligence

• With the coming availability of low cost, short
  range radios along with advances in wireless
  networking, it is expected that wireless ad hoc
  sensor networks will become commonly
  deployed...Each node may have sufficient
  processing power to make a decision, and it will
  be able to broadcast this decision to the other
  nodes in the cluster.  One node may act as the
  cluster master, and it may also contain a longer
  range radio using a protocol such as IEEE 802.11
  or Bluetooth -- http//w3.antd.nist.gov/wahn_ssn.s
  html

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Processor Performance
IV. Current technology trends and COTS Processor
Scalability
84
BlueGene/L
IV. Current technology trends and COTS Processor
Scalability

• 360 peak teraOPS (TOPS)
• 1,024 nodes (2,048 processors) 5
  teraOPS/air-cooled cabinet
• 32 Tbytes memory
• 1.5 megawatts
• 2,500 square feet
• The full system has 65,536 dual-processor compute
  nodes

85
BlueGene/L Technology
IV. Current technology trends and COTS Processor
Scalability
86
CELL
IV. Current technology trends and COTS Processor
Scalability
87
WSN microtransmitters
V. Current technology trends and COTS COTS
Wireless Sensing

• Small outline digital wireless sensor node
• 30mW power when transmitting, 15 microwatts when
  sleeping
• AA Li-Ion battery life 2-5 years
• Wireless networking protocol implemented in
  firmware
• 16 bit A/D resolution
• Transmission range 1/3 mile LOS

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G-Link COTS Wireless Sensor Node
89
Microstrain G-Link
V. Current technology trends and COTS COTS
Wireless Sensing
58 mm

• Supports simultaneous streaming from multiple
  nodes to PC
• Available with 2g or 10g range
• Datalogging rates up to 2048 Hz
• Real-time streaming rates up to 736 Hz
• On-board memory stores up to 1,000,000
  measurements
• Communication range up to 70m line-of-sight
• Low power consumption for extended use

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Net - Internet
91
Discussion of ECE-994 Project

• Major portion of the ECE-994
• Should relate to the technical material in the
  course i.e. PSOC or FPGA
• Should be based and take full advantage of the
  XUP Development Kit
• Should be related to the work of the Rucinski
  Group and the CIDL
• Is most successful when it involves all
  collaboratively

92
ECE-994 Project

• A major focus of CIDL and Rucinski Group is on
  Distributed Sensor Networks that feature
• Ad-hoc robust and efficient network capability
• coming and going of nodes without a reboot
• Self organization or self reorganization to
  optimize performance
• Distributed processing and storage
• Capability of interfacing with many types of
  sensors
• Based on standards and opensource as much as
  possible
• Maximal adaptability, reconfigurability to serve
  many possible applications in security and safety

93
ECE-994 Project Ideas

• Building a concept demo of a generic node in a
  sensor network
• Combine core FPGA for control and processing with
  external
• sensors
• A/D such as the Digilent AIO1
• http//www.digilentinc.com/Products/Detail.cfm?Pro
  dAIO1Nav1ProductsNav2Accessory
• Communications
• Based on MPI for network OS and coordination

94
ECE-994 ProjectTasks

• Form the team chose a team leader
• Research the XUP Development Kit
• Decide on a preferred project and a back-up
• Decide on who is responsible for what aspect and
  the timetable
• Develop your formal Project Proposal and
• be prepared to formally present it

95
Ambient Node in an Intelligent Network
Applications
V. Applications Current Ambient Designs

• Web Interrogation / U.S. Virtual Sea Border -NI2
  Project
• PLUTO -- Tunnel, Mine Monitoring System Project
• Ocean Deep Underwater Research Project
• Intelligent Communication Network Project

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Ambient Node in an Intelligent Network US Virtual
Sea Border Project
V. Applications Current Ambient Designs

• Phase I Interactive Communication Link ICL -
  (secure chat audio/video communication between
  captain deck and command control third party)
• Phase II Security Managements System - SMS - (
  phase I the management system with container
  communication, Node availability checking,
  Graphical interface for command control and
  website access for the end users (like cargo,
  ship, etc, owners))
• Phase III Ambient Security Control System -
  ASCS ( phase II more node sophisticated sensors
  with node display and portable controller
  scanners for investigation team)

   NI2 Center for Infrastructure Expertise
97
ApplicationsU.S. Virtual Sea Border Project -
phase III
V. Applications Current Ambient Designs
WAN
Alarm Availability
   NI2 Center for Infrastructure Expertise
98
Container Security System Design Criteria
V. Applications Current Ambient Designs

• Distributed processing minimizes need for on the
  air bandwidth and lowers system power
  consumption
• Each device has unique address, network is ad
  hoc
• Node based data storage for storing dynamic
  waveforms
• Capable of deployment of over 1000 nodes, using
  one RF transmission frequency to one receiver
• Small size, easy to place in the field
• Low power, long battery life
• Long transmission range
• Capable of automated Internet data delivery

99
Container Security System Architecture
V. Applications Current Ambient Designs

• Encrypted digital data is transmitted via a TDMA
  wireless network (1/3 mile range), to a local
  receiver
• An 802.11b hierarchical, spoke-and-hub receiver
  network (1-2 mile range), enables monitoring of
  thousands of individual sensors and containers
• Additional Features
• Advanced signal processing
• Geolocation
• Intelligent triggering
• Local storage
• Local interrogation with portable receivers.

100
Conceptual Block Diagram
V. Applications Current Ambient Designs
presented at SiCon 02 S.W. Arms, T.P. Kochanski,
et. al.
101
Concept of PLUTO
V. Applications New directions Projects PLUTO

• Satisfy requirement for flexible, accessible
  testbed to
• Gather experimental data for validation
• Develop and test operational sensors
• Platform Laboratory for Underground and Tunnel
  Observations
• Use an experimental underground mine as a
  laboratory to perform experiments to model mines
  and tunnels
• Polands Central Mining Institute operates the
  Experimental Mine Barbara that provides an
  ideal testbed
• George Markowsky et. al., "Anywhere, Anytime,
  Any Size, Any Signal Scalable, Remote
  Information Sensing and Communication Systems",
  2002
• Kazimierz Lebecki, "Zagrozenia Pylowe w
  Górnictwie", 2004

102
PLUTO
V. Applications New directions Projects PLUTO

• Platform
• Internet accessible
• Laboratory
• Virtual
• Underground
• Experimental Mine Barbara
• Tunnel
• And mine related
• Observations
• Experiments
• Modeling
• Sensor evaluation and testing

103
Schematic Diagram of Experimental Gallery
V. Applications New directions Projects PLUTO

• Dense array of wireless sensor units for
• Pressure
• Temperature
• Optical Radiation
• Combined with some sensors to determine chemical
  composition

Wireless Access Point connected to Optical
Backbone
Mobile robotic sensor vehicle
104
V. Applications New directions Projects PLUTO
Experimental Mine Barbara
Virtual Mine Barbara
Gdansk
105
Node Architecture - SoC
V. Applications New directions SOC Architecture

• Technology
• FPGA Xillinx, Altera, Actel
• Functions
• (Capabilities / IP Cores)
• Wireless communication
• Cryptography
• Management
• Internet Protocol Signalization
• I/O bus - sensors

Wireless Antenna 1
Wireless Antenna 2
Switch
Communication
FPGA SoC
Management
Cryptography
CPU
I/O bus
Digital Lock
External sensors
GPS
106
Architecture Node FPGA Implementation
V. Applications New directions SOC Architecture
107
Ambient Node in an Intelligent Network
Applications Future Steps
V. Applications New directions Future Steps

• Ambient Network
• Power Management
• Signalization of Sensors Network
• Inter-network communication
• Node Addressing
• US VSB Project
• Cargo container anomalies specification
• Procedures Countermeasures

108
Sensor Networking and Synthetic RealityOutline

• I. Introduction and definitions
• II. Key pieces of the core technology
• III 1950s digital sensor networking
• IV. Current off the shelf technology
• V Applications
• VI. Areas that still need lots of work and the
  future
• VII. Conclude

109
Key Technical Challenges

• VI. Areas that still need lots of work and the
  future

• Efficient networking configuration and routing
• To enable rapid, ad hoc networking of any number
  of either fixed or mobile devices
• Collaborative signal and information processing
• To detect, classify, and track events and
  localized patterns of events
• Distributed microdatabases over a spatio-temporal
  interval
• Stored in the devices
• Queriable by multiple users
• Methods for dynamic programmability of the
  network
• Methods for security and information assurance to
  enable
• Intrusion detection, intrusion tolerance, and
  survivable operation in the face of failure and
  compromise
• Power efficient elements
• Interactive, dynamic fully-immersive, real-time
  access
• Middleware for remote, secure, control and access
• User-friendly development tools for the
  applications creators

110
What of the future?Highly speculative no
promises
VI. Areas that still need lots of work and the
future

• Sensors with great sensitivity, specificity and
  flexibility
• Nano-scale and meso-scale?
• Fully integrated plug and play sensor modules
  with signal processing, storage and
  communications in a single package
• Global, collaborative real-time access to sensor
  networks
• Sensors that know what you want to find out and
  can be your friend

111
Sensor Networking and Synthetic RealityOutline

• I. Introduction and definitions
• II. Fundamentals of sensors and signals
• III. Key pieces of the core technology
• IV. Project Lincoln
• 1950s digital sensor networking and synthetic
  reality
• V. Current off the shelf technology
• VI. New directions Projects NEPTUNE, VLAB, PLUTO
  
• VII. Areas that still need lots of work and the
  future
• VII. Conclude

112
Some Observations

• VII. Conclude

• System perspective is critical to success
• Only as good as integrated hw / sw
• Reusability modularity of hardware
• Reusability modularity of software
• Software is far behind Hardware in
  price/performance, improvement/decade\
• Lacking Easy to use Tools for Wireless
  Communications
• Design, Implementation and Testing
• Need for collaboration on all scales
• Synergistic Model MIT Model Combine
• University fundamental r and concept d,
  education and training
• with industrial applied rd
• And entrepreneurial funding sources

113
References Links
VII. Conclude

• Ambient Intelligence http//ambient.media.mit.edu
  /vision.html, http//courses.media.mit.edu/2005spr
  ing/mas961/readings.html,
• Signal Processing http//www.techonline.com/commu
  nity/ed_resource/20771, http//www.dspguide.com/pd
  fbook.htm
• NIST Sensor Networks http//w3.antd.nist.gov/wahn
  _ssn.shtml
• Blue Gene http//www.internetnews.com/ent-news/ar
  ticle.php/3432221
• Cell Processor http//cell.scei.co.jp/index_e.htm
  l, http//www.mc.com/products/view/index.cfm?id96
  typeboards
• Bluetooth http//www.bluetooth.com/bluetooth/
• NEPTUNE, etc.http//www.whoi.edu/mr/pr.do?id1578
  
• CAVE http//www.cs.vu.nl/7Erenambot/vr/cases/mol
  .htm, http//www.evl.uic.edu/pape/CAVE/
• Fledermaushttp//www.ivs3d.com/products/technolog
  y/thebat.html
• More VR http//www.sgvl.geo.su.se/index.php?optio
  ncom_contenttaskviewid42Itemid148,
  http//www.ccom-jhc.unh.edu/, http//archive.ncsa.
  uiuc.edu/Cyberia/VETopLevels/VR.Interface.html,
  http//www.ccom.unh.edu/vislab/CenterofWorkspaceIn
  teraction.mov http//www.research.ibm.com/journal
  /sj/393/part3/paradiso.html
• VLAB http//vlab.psnc.pl/gen_info.html
• MIT ILAB http//icampus.mit.edu/ilabs/
• Central Mining Institute http//www.gig.katowice.
  pl/gig/index_english.php
• Microstrain Wireless Modules http//www.microstra
  in.com/2400g-link_specs.aspx
• MIT Project Oxygen http//oxygen.lcs.mit.edu/Kno
  wledgeAccess.html
• SAGE, Project Lincoln http//www.mitre.org/about/
  photo_archives/sage_photo.html

114
CONTACT INFO

• VII. Conclude

• University of New Hampshire, Durham, NH, USA
• Thaddeus Paul Kochanski, Ph.D.
• Tel [phone]
• tpz4_at_unh.edu
• tedpk_at_alum.mit.edu
• Andrzej Rucinski, Ph.D.
• Tel [phone]
• andrzej.rucinski_at_unh.edu
• Central Mining Institute, Katowice, Poland
• Kazimierz Lebecki, D.Sc.
• Tel [phone], mobile [phone]
• kazimierz.lebecki_at_neostrada.pl
• http//www.gig.katowice.pl/gig/index_english.php

115
Thank You

• Muchas Gracias
• Dziekuje za uwage

116
Thanks
117
END Presentation

• Following slides for backup only
• DO NOT PRINT

118
CELL