Digital Integrated Circuits A Design Perspective

1
Digital Integrated CircuitsA Design Perspective
Designing CombinationalLogic Circuits
November 2002.
2
Combinational vs. Sequential Logic
In
Out
In
Out
Combinational
Sequential
Output
(
)
f
In, Previous In
Output
(
)
f
In
3
Static CMOS Circuit
4
Static Complementary CMOS
VDD
In1
PMOS only
In2
PUN

InN
F(In1,In2,InN)
In1
In2
PDN

NMOS only
InN
PUN and PDN are dual logic networks
5
NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled
by its gate signal NMOS switch closes when switch
control input is high
6
PMOS Transistors in Series/Parallel Connection
7
Threshold Drops
VDD
VDD
PUN
S
D
VDD
D
S
0 ? VDD
0 ? VDD - VTn
VGS
VDD ? 0
PDN
VDD ? VTp
VGS
S
D
VDD
S
D
8
Complementary CMOS Logic Style
9
Example Gate NAND
10
Example Gate NOR
11
Complex CMOS Gate
OUT D A (B C)
A
D
B
C
12
Cell Design

• Standard Cells
• General purpose logic
• Can be synthesized
• Same height, varying width
• Datapath Cells
• For regular, structured designs (arithmetic)
• Includes some wiring in the cell
• Fixed height and width

13
Standard Cells
N Well
Cell height 12 metal tracks Metal track is
approx. 3? 3? Pitch repetitive distance
between objects Cell height is 12 pitch
Out
In
2?
Rails 10?
GND
Cell boundary
14
Standard Cells
2-input NAND gate
A
B
Out
GND
15
Stick Diagrams
Contains no dimensions Represents relative
positions of transistors
Inverter
NAND2
Out
Out
In
A
B
GND
GND
16
Stick Diagrams
Logic Graph
A
C
j
B
X C (A B)
C
i
A
B
A
B
C
17
Two Stick Layouts of !(C (A B))
18
Consistent Euler Path

• An uninterrupted diffusion strip is possible only
  if there exists a Euler path in the logic graph
• Euler path a path through all nodes in the graph
  such that each edge is visited once and only once.

X
C
VDD
i
X
A
B
j
A
B
C
GND

• For a single poly strip for every input signal,
  the Euler paths in the PUN and PDN must be
  consistent (the same)

19
Example1. Draw Logic Graph

• Identify each transistor by a unique name of its
  gate signal (A, B, C, D, E in the example of
  Figure 1).
• Identify each connection to the transistor by a
  unique name (1,2,3,4 in the example of Figure 1).

20
Example2. Define Euler Path

• Euler paths are defined by a path the traverses
  each node in the path, such that each edge is
  visited only once.
• The path is defined by the order of each
  transistor name. If the path traverses transistor
  A then B then C. Then the path name is A, B, C
• The Euler path of the Pull up network must be the
  same as the path of the Pull down network.
• Euler paths are not necessarily unique.
• It may be necessary to redefine the function to
  find a Euler path. F E (CD) (AB) (AB) E
  (CD)

21
Example3.Connection label layout
22
Example4.VDD, VSS and Output Labels
23
Example5.Interconnected
24
OAI22 Logic Graph
X
PUN
A
C
C
D
B
D
VDD
X
X (AB)(CD)
C
D
A
B
A
B
PDN
A
GND
B
C
D
25
Example x abcd
26
CMOS Properties

• Full rail-to-rail swing high noise margins
• Logic levels not dependent upon the relative
  device sizes ratioless
• Always a path to Vdd or Gnd in steady state low
  output impedance
• Extremely high input resistance nearly zero
  steady-state input current
• No direct path steady state between power and
  ground no static power dissipation
• Propagation delay function of load capacitance
  and resistance of transistors

27
Switch Delay Model
Req
A
A
NOR2
INV
NAND2
28
Input Pattern Effects on Delay

• Delay is dependent on the pattern of inputs
• Low to high transition
• both inputs go low
• delay is 0.69 Rp/2 CL
• one input goes low
• delay is 0.69 Rp CL
• High to low transition
• both inputs go high
• delay is 0.69 2Rn CL

Rn
B
29
Delay Dependence on Input Patterns
AB1?0
A1 ?0, B1
A1, B1?0
Voltage V
time ps
NMOS 0.5?m/0.25 ?m PMOS 0.75?m/0.25 ?m CL
100 fF
30
Transistor Sizing

4 4
2 2
31
Transistor Sizing a Complex CMOS Gate
B
8
6
4
3
C
8
6
4
6
OUT D A (B C)
A
2
D
1
B
C
2
2
32
Fan-In Considerations
A
Distributed RC model
(Elmore delay) tpHL 0.69 Reqn(C12C23C34CL)
Propagation delay deteriorates rapidly as a
function of fan-in quadratically in the worst
case.
B
C
D
33
tp as a Function of Fan-In
Gates with a fan-in greater than 4 should be
avoided.
tp (psec)
tpLH
fan-in
34
tp as a Function of Fan-Out
All gates have the same drive current.
tpNOR2
tpNAND2
tpINV
tp (psec)
Slope is a function of driving strength
eff. fan-out
35
tp as a Function of Fan-In and Fan-Out

• Fan-in quadratic due to increasing resistance
  and capacitance
• Fan-out each additional fan-out gate adds two
  gate capacitances to CL
• tp a1FI a2FI2 a3FO

36
Fast Complex GatesDesign Technique 1

• Transistor sizing
• as long as fan-out capacitance dominates
• Progressive sizing

Distributed RC line M1 gt M2 gt M3 gt gt MN (the
fet closest to the output is the smallest)
InN
MN
In3
M3
In2
M2
Can reduce delay by more than 20 decreasing
gains as technology shrinks
In1
M1
37
Fast Complex GatesDesign Technique 2

• Transistor ordering

critical path
critical path
0?1
charged
charged
In1
1
In3
M3
M3
1
In2
1
In2
M2
discharged
M2
charged
1
In3
discharged
In1
M1
charged
M1
0?1
delay determined by time to discharge CL, C1 and
C2
delay determined by time to discharge CL
38
Fast Complex GatesDesign Technique 3

• Alternative logic structures

F ABCDEFGH
39
Fast Complex GatesDesign Technique 4

• Isolating fan-in from fan-out using buffer
  insertion

40
Fast Complex GatesDesign Technique 5

• Reducing the voltage swing
• linear reduction in delay
• also reduces power consumption
• But the following gate is much slower!
• Or requires use of sense amplifiers on the
  receiving end to restore the signal level (memory
  design)

tpHL 0.69 (3/4 (CL VDD)/ IDSATn )
0.69 (3/4 (CL Vswing)/ IDSATn )
41
Ratioed Logic
42
Ratioed Logic
43
Ratioed Logic
44
Active Loads
45
Pseudo-NMOS
46
Pseudo-NMOS VTC
3.0
2.5
W/L
4
2.0
p
1.5
V

W/L
2
t
u
p
o
V
1.0
W/L
0.5
W/L
1
p
p
0.5
W/L
0.25
p
0.0
0.0
0.5
1.0
1.5
2.0
2.5
V
V
in
47
Improved Loads
48
Improved Loads (2)
V
V
DD
DD
M1
M2
Out
Out
A
A
PDN1
PDN2
B
B
V
V
SS
SS
Differential Cascode Voltage Switch Logic (DCVSL)
49
DCVSL Example
50
DCVSL Transient Response
A B
V
e
A B
g
a
t
l
o
A
,
B
V
A,B
Time ns
51
Pass-TransistorLogic
52
Pass-Transistor Logic
53
NMOS-Only Logic
3.0
In
Out
2.0
V
x

e
g
a
t
l
o
V
1.0
0.0
0
0.5
1
1.5
2
Time ns
54
NMOS-only Switch
V
C
2.5 V
C
2.5

M
2
A
2.5 V
B
A
2.5 V
M
n
B
M
C
1
L
does not pull up to 2.5V, but 2.5V -
V
V
TN
B
Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
55
NMOS Only Logic Solution 1 Level Restoring
Transistor
V
DD
V
DD
Level Restorer
M
r
B
M
2
X
M
A
Out
n
M
1
Advantage Full Swing
Restorer adds capacitance, takes away pull down
current at X
Ratio problem
56
Solution 2 Single Transistor Pass Gate with VT0
V
DD
V
DD
0V
2.5V
Out
0V
V
DD
2.5V
WATCH OUT FOR LEAKAGE CURRENTS
57
Complementary Pass Transistor Logic
58
Solution 3 Transmission Gate
C
C
A
A
B
B
C
C
C
2.5 V
A
2.5 V
B
C
L
C

0 V
59
Resistance of Transmission Gate
60
Pass-Transistor Based Multiplexer
S
VDD
GND
In1
In2
S
61
Transmission Gate XOR
B
B
M2
A
A
F
M1
M3/M4
B
B
62
Transmission Gate Full Adder
Similar delays for sum and carry
63
Dynamic Logic
64
Dynamic CMOS

• In static circuits at every point in time (except
  when switching) the output is connected to either
  GND or VDD via a low resistance path.
• fan-in of n requires 2n (n N-type n P-type)
  devices
• Dynamic circuits rely on the temporary storage of
  signal values on the capacitance of high
  impedance nodes.
• requires on n 2 (n1 N-type 1 P-type)
  transistors

65
Dynamic Gate
Mp
Clk
Out
In1
In2
PDN
In3
Me
Clk
Two phase operation Precharge (CLK 0)
Evaluate (CLK 1)
66
Dynamic Gate
off
Mp
Clk
on
1
Out
In1
In2
PDN
In3
Me
Clk
off
on
Two phase operation Precharge (Clk 0)
Evaluate (Clk 1)
67
Conditions on Output

• Once the output of a dynamic gate is discharged,
  it cannot be charged again until the next
  precharge operation.
• Inputs to the gate can make at most one
  transition during evaluation.
• Output can be in the high impedance state during
  and after evaluation (PDN off), state is stored
  on CL

68
Properties of Dynamic Gates

• Logic function is implemented by the PDN only
• number of transistors is N 2 (versus 2N for
  static complementary CMOS)
• Full swing outputs (VOL GND and VOH VDD)
• Faster switching speeds
• reduced load capacitance due to lower input
  capacitance (Cin)
• reduced load capacitance due to smaller output
  loading (Cout)
• no Isc, so all the current provided by PDN goes
  into discharging CL
• Overall power dissipation usually higher than
  static CMOS
• Low noise margin (NML)
• Needs a precharge/evaluate clock

69
Issues in Dynamic Design 1 Charge Leakage
CLK
Clk
Mp
Out
A
Evaluate
VOut
Clk
Me
Precharge
Leakage sources
Dominant component is subthreshold current
70
Solution to Charge Leakage
Keeper
Clk
Mp
Mkp
A
Out
B
Clk
Me
Same approach as level restorer for
pass-transistor logic
71
Issues in Dynamic Design 2 Charge Sharing
Charge stored originally on CL is redistributed
(shared) over CL and CA leading to reduced
robustness
Clk
Mp
Out
A
B0
Clk
Me
72
Charge Sharing Example
Clk
Out
A
A
B
B
B
!B
C
C
Clk
73
Charge Sharing
V
DD
M
Clk
p
Out
C
L
A
M
a
X
C
a

M
B
0
b
C
b
M
Clk
e
74
Solution to Charge Redistribution
Clk
Clk
Mp
Mkp
Out
A
B
Clk
Me
Precharge internal nodes using a clock-driven
transistor (at the cost of increased area and
power)
75
Issues in Dynamic Design 3 Backgate Coupling
Clk
Mp
Out1
1
Out2
0
In
A0
B0
Clk
Me
Dynamic NAND
Static NAND
76
Backgate Coupling Effect
Out1
Voltage
Clk
Out2
In
Time, ns
77
Issues in Dynamic Design 4 Clock Feedthrough
Coupling between Out and Clk input of the
precharge device due to the gate to drain
capacitance. So voltage of Out can rise above
VDD. The fast rising (and falling edges) of the
clock couple to Out.
Clk
Mp
Out
A
B
Clk
Me
78
Clock Feedthrough
Clock feedthrough
Clk
Out
In1
In2
In3
In Clk
Voltage
In4
Out
Clk
Time, ns
Clock feedthrough
79
Other Effects

• Capacitive coupling
• Substrate coupling
• Minority charge injection
• Supply noise (ground bounce)

80
Cascading Dynamic Gates
V
Clk
Clk
Mp
Mp
Out2
Out1
In
Clk
Clk
Me
Me
t
Only 0 ? 1 transitions allowed at inputs!
81
Domino Logic
Mp
Clk
Mkp
Mp
Clk
Out1
Out2
1 ? 1 1 ? 0
0 ? 0 0 ? 1
In1
In4
PDN
In2
PDN
In5
In3
Me
Clk
Me
Clk
82
Why Domino?
Clk
Clk
Like falling dominos!
83
Properties of Domino Logic

• Only non-inverting logic can be implemented
• Very high speed
• static inverter can be skewed, only L-H
  transition
• Input capacitance reduced smaller logical
  effort

84
Designing with Domino Logic
V
V
DD
DD
V
DD
Clk
M
Clk
M
p
p
M
r
Out1
Out2
In
1
PDN
In
PDN
In
2
4
In
3
Can be eliminated!
M
Clk
M
Clk
e
e
Inputs 0 during precharge
85
np-CMOS
Me
Clk
Mp
Clk
Out1
1 ? 1 1 ? 0
In4
PUN
In1
In5
In2
PDN
0 ? 0 0 ? 1
In3
Out2 (to PDN)
Mp
Clk
Me
Clk
Only 0 ? 1 transitions allowed at inputs of PDN
Only 1 ? 0 transitions allowed at inputs of PUN